Internal voltage generation device

Patent metadata

Field	Value
Publication number	US-2016349784-A1
Application number	US-201514873597-A
Country	US
Kind code	A1
Filing date	Oct 2, 2015
Priority date	May 26, 2015
Publication date	Dec 1, 2016
Grant date	—

Abstract

An internal voltage generation device includes a voltage generation block configured to compare a reference voltage and a divided voltage, and generate an output voltage; and an internal voltage driving block including a pull-up driving unit which selectively pull-up drives an internal voltage according to the output voltage, and configured to output the output voltage to the pull-up driving unit through different paths according to a test signal.

First claim

What is claimed is:

1 . An internal voltage generation device comprising:
a voltage generation block configured to compare a reference voltage and a divided voltage, and generate an output voltage; and an internal voltage driving block including a pull-up driving unit which selectively pull-up drives an internal voltage according to the output voltage, and configured to output the output voltage to the pull-up driving unit through different paths according to a test signal.

2 . The internal voltage generation device according to claim 1 , wherein the voltage generation block comprises:
a comparison unit configured to compare the reference voltage and the divided voltage; a biasing unit configured to supply a biasing voltage to the comparison unit; and a driving unit configured to drive an output of the comparison unit and output the output voltage.

3 . The internal voltage generation device according to claim 1 , wherein the internal voltage driving block comprises:
a test control unit configured to drive the test signal and output a first signal and a second signal; a digital driving unit configured to control the output voltage to a logic level according to an output of the test control unit, and output the logic level to the pull-up driving unit; and an analog driving unit configured to output the output voltage to the pull-up driving unit according to the output of the test control unit.

4 . The internal voltage generation device according to claim 3 , wherein the test control unit comprises:
a first inverter configured to invert the test signal; and a second inverter configured to invert an output of the first inverter.

5 . The internal voltage generation device according to claim 3 , wherein the digital driving unit and the analog driving unit operate complementarily to each other.

6 . The internal voltage generation device according to claim 3 , wherein, in the internal voltage driving block, the digital driving unit operates where the test signal is a high level, and the analog driving unit operates where the test signal is a low level.

7 . The internal voltage generation device according to claim 3 , wherein, in the internal voltage driving block, the analog driving unit is floated where the test signal is a high level, and the digital driving unit is floated where the test signal is a low level.

8 . The internal voltage generation device according to claim 3 , wherein the digital driving unit outputs a signal corresponding to a level of the output voltage to the pull-up driving unit where the test signal is a high level, and is floated where the test signal is a low level.

9 . The internal voltage generation device according to claim 4 , wherein the digital driving unit comprises:
a first NAND gate configured to perform a NAND logic function on the second signal and the output voltage; and a third inverter configured to invert an output of the first NAND gate in correspondence to the first signal and the second signal.

10 . The internal voltage generation device according to claim 9 , wherein the third inverter is a tri-state inverter.

11 . The internal voltage generation device according to claim 9 , wherein the third inverter comprises:
a first PMOS transistor configured to pull-up drive a power supply voltage in correspondence to the output of the first NAND gate; a first NMOS transistor configured to pull-down drive a ground voltage in correspondence to the output of the first NAND gate; a second PMOS transistor electrically coupled between the first PMOS transistor and an output terminal of the third inverter, and configured to be controlled by the first signal; and a second NMOS transistor electrically coupled between the first NMOS transistor and the output terminal of the third inverter, and configured to be controlled by the second signal.

12 . The internal voltage generation device according to claim 11 , wherein, in the third inverter, the second PMOS transistor and the second NMOS transistor are turned on when the test signal is a high level, and the first PMOS transistor and the first NMOS transistor are selectively turned on in correspondence to the output voltage.

13 . The internal voltage generation device according to claim 11 , wherein, in the third inverter, the second PMOS transistor and the second NMOS transistor are turned off when the test signal is a low level, and the third inverter is floated.

14 . The internal voltage generation device according to claim 3 , wherein the analog driving unit comprises a transmission gate configured to be selectively turned on in correspondence to the first signal and the second signal and transfer the output voltage.

15 . The internal voltage generation device according to claim 14 , wherein the analog driving unit outputs the output voltage to the pull-up driving unit where the test signal is a low level, and is floated where the test signal is a high level.

16 . The internal voltage generation device according to claim 1 , wherein the internal voltage driving block further comprises:
a voltage division unit configured to divide the internal voltage and output the divided voltage.

17 . The internal voltage generation device according to claim 16 , wherein the pull-up driving unit comprises a third PMOS transistor configured to supply the power supply voltage to an output terminal of the internal voltage in correspondence to the output voltage.

18 . The internal voltage generation device according to claim 1 , wherein the test signal is a signal which varies in correspondence to a level of a power supply voltage.

19 . An internal voltage generation device comprising:
a voltage generation block configured to compare a reference voltage and a divided voltage, and generate an output voltage; a pull-up driving unit configured to selectively pull-up drive an internal voltage according to the output voltage; a test control unit configured to drive a test signal; a digital driving unit configured to control the output voltage to a logic level according to an output of the test control unit, and output the logic level to the pull-up driving unit; and an analog driving unit configured to output the output voltage to the pull-up driving unit according to the output of the test control unit.

20 . The internal voltage generation device according to claim 19 , wherein the digital driving unit and the analog driving unit operate complementarily to each other in correspondence to the test signal.

21 . An internal voltage generation device comprising:
a voltage generation block configured to generate an output voltage and amplify a resultant signal and output the output voltage; and an internal voltage driving block configured to receive the output voltage and pull-up drive a power supply voltage according to an output of a digital driving unit and an output of an analog driving unit.

22 . The internal voltage generation device according to claim 21 , wherein an internal voltage with a lower potential than an external supply voltage is used in a core region.

23 . The internal voltage generation device according to claim 21 , wherein the digital driving unit and the analog driving unit are selected according to a test signal.

24 . The internal voltage generation device according to claim 23 , wherein the test signal is a signal for sensing a level of the power supply voltage.

25 . The in

Assignees

• Sk Hynix Inc

Inventors

• Kim Yeon Uk

Classifications

• G05F1/465

  Internal voltage generators for integrated circuits, e.g. step down generators · CPC title

• G05F1/462

  as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic · CPC title

• G05F3/02

  Regulating voltage or current · CPC title

• G05F1/575

  characterised by the feedback circuit · CPC title

• G05F1/10

  Regulating voltage or current  (G05F1/02 takes precedence) · CPC title