Charge pump apparatus

Patent metadata

Field	Value
Publication number	US-2016006348-A1
Application number	US-201414505506-A
Country	US
Kind code	A1
Filing date	Oct 3, 2014
Priority date	Jul 7, 2014
Publication date	Jan 7, 2016
Grant date	—

Abstract

The invention provides a charge pump apparatus including a clock signal generator, a clock freezing circuit, a charge pump circuit, and a feedback circuit. The clock signal generator generates a clock signal. The clock freezing circuit directly receives the clock signal and an enable signal. The clock freezing circuit decides whether to pass or latch a voltage level of the clock signal according to the enable signal to generate a controlled clock signal. The charge pump circuit directly receives the controlled clock signal and operates a charge pump operation on an input voltage to generate a pumping voltage.

First claim

What is claimed is:

1 . A charge pump apparatus, comprising:
a clock signal generator, generating a clock signal; a clock freezing circuit, coupled to the clock signal generator, directly receiving the clock signal and an enable signal, and deciding whether to pass a voltage level of the clock signal or not according to the enable signal for generating a controlled clock signal; a charge pump circuit, coupled to the clock freezing circuit, directly receiving the controlled clock signal and operating a charge pump operation on an input voltage to generate a pumping voltage; and a feedback circuit, coupled to the charge pump circuit and the clock freezing circuit, wherein the feedback circuit compares the pumping voltage and a preset target voltage to generate the enable signal.

2 . The charge pump apparatus as claimed in claim 1 , wherein the feedback circuit generates the enable signal with a first logic level when the pumping voltage is lower than the preset target voltage, and the feedback circuit generates the enable signal with a second logic level when the pumping voltage is higher than the preset target voltage,
wherein the first logic level and the second logic level are complementary.

3 . The charge pump apparatus as claimed in claim 2 , wherein the clock freezing circuit passes the voltage level of the clock signal to generate the controlled clock signal when the enable signal is at the first logic level.

4 . The charge pump apparatus as claimed in claim 3 , wherein the clock freezing circuit generates the controlled clock signal by latching the clock signal at a time point for the enable signal transited from the first logic level to the second logic level.

5 . The charge pump apparatus as claimed in claim 4 , wherein the clock freezing circuit comprises:
a latch circuit, receives the clock signal and the enable signal, and decide whether to latch the clock signal or not to generated the controlled clock signal according to the enable signal.

6 . The charge pump apparatus as claimed in claim 5 , wherein the latch circuit comprises:
a first inverter, receives the clock signal and generates an inverted clock signal; a switch, has a first end for receiving the inverted clock signal, and controlled by the enable signal to be turned on or turned off; a second inverter, has a input end coupled to a second end of the switch, and an output end of the second inverter generates the controlled clock signal; and a tri-state inverter, has an input end, an output end and a control end, wherein the output end of the tri-state inverter is coupled to the second end of the switch, the input end of the tri-state inverter is coupled to the output end of the second inverter, and the control end of the tri-state inverter receives the enable signal.

7 . The charge pump apparatus as claimed in claim 5 , wherein the switch is a transmission gate, and a first end of the transmission gate receives the inverted clock signal, a second end of the transmission gate is coupled to the input end of the second inverter, and a first and second control ends of the transmission gate respectively receive the enable signal and a inverted enable signal.

8 . The charge pump apparatus as claimed in claim 1 , wherein the feedback circuit comprises:
a voltage regulator, receives the pumping voltage and generated a compared voltage according to the pumping voltage; and a comparator, coupled to the voltage regulator and the clock freezing circuit, and the comparator compares the compared voltage and the preset target voltage to generate the enable signal.

9 . The charge pump apparatus as claimed in claim 1 , wherein the clock signal generator further receives the enable signal, and the clock signal generator decides whether to generate the clock signal or not according to the enable signal.

10 . The charge pump apparatus as claimed in claim 1 , wherein the charge pump circuit comprises at least one capacitor, and the controlled clock signal is directly connected to the at least one capacitor.

11 . The charge pump apparatus as claimed in claim 1 , wherein the clock signal comprises a first, second, third and fourth sub-clock signals, and the phases of the first, second, third and fourth sub-clock signals are different.

12 . The charge pump apparatus as claimed in claim 1 , wherein the clock signal generator is a ring oscillator.

Assignees

• Ememory Technology Inc

Inventors

• Ho Hsin-Liang
• Chang Wu-Chang

Classifications

• H02M1/14

  Arrangements for reducing ripples from DC input or output · CPC title

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• G11C5/145 Primary

  Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence) · CPC title

• G11C16/12

  Programming voltage switching circuits · CPC title

• G11C16/30

  Power supply circuits · CPC title