Manufacturing method of low temperature polysilicon thin film transistor

Patent metadata

Field	Value
Publication number	US-2016343829-A1
Application number	US-201514425052-A
Country	US
Kind code	A1
Filing date	Jan 16, 2015
Priority date	Dec 16, 2014
Publication date	Nov 24, 2016
Grant date	—

Abstract

The invention provides a manufacturing method of a low temperature polysilicon thin film transistor, including: providing a substrate; forming a buffer layer on the substrate; simultaneously forming a polysilicon layer and a photoresist layer on the buffer layer; implanting ions into a source region and a drain region; removing the photoresist layer; forming an insulating layer on the polysilicon layer; forming a gate electrode on the insulating layer; and forming a passivation layer on the insulating layer. The passivation layer covers the gate electrode. The invention can only use one time of mask process and one time of ion implantation process to complete the manufacturing processing of the polysilicon layer, the manufacturing process can be simplified and therefore the cost of process is reduced and the productivity is improved.

First claim

What is claimed is:

1 . A manufacturing method of a low temperature polysilicon thin film transistor, comprising:
providing a substrate; forming a buffer layer on the substrate; simultaneously forming a polysilicon layer and a photoresist layer on the buffer layer, wherein the polysilicon layer comprises a source region, a drain region and a channel region located therebetween; a thickness of the photoresist layer located on a portion of the source region far away from the channel region, a thickness of the photoresist layer located on a portion of the source region close to the channel region and a thickness of the photoresist layer located on the channel region are successively increased in that order; a thickness of the photoresist layer located on a portion of the drain region far away from the channel region, a thickness of the photoresist layer located on a portion of the drain region close to the channel region and the thickness of the photoresist layer located on the channel region are successively increased in that order; implanting ions into the source region and the drain region to make the source region and the drain region to form a source electrode and a drain electrode respectively, wherein a portion of the source region far away from the channel region is a source heavily doped region, a portion of the source region close to the channel region is a source lightly doped region, a portion of the drain region far away from the channel region is a drain heavily doped region, a portion of the drain region close to the channel region is a drain lightly doped region; removing the photoresist layer; forming an insulating layer on the polysilicon layer; forming a gate electrode on the insulating layer; forming a passivation layer on the insulating layer, wherein the passivation layer is disposed covering the gate electrode.

2 . The manufacturing method according to claim 1 , wherein simultaneously forming a polysilicon layer and a photoresist layer comprises: forming a polysilicon on a surface of the buffer layer, forming a photoresist material on a surface of the polysilicon by spin coating, using a predetermined mask to perform an exposure on the photoresist material, developing the photoresist material after the exposure, remaining the polysilicon and the photoresist material in the region where the polysilicon layer and the photoresist layer are formed and removing the polysilicon and the photoresist material in the other location,
wherein a transmittance of a region of the predetermined mask opposing to the channel region, a transmittance of a region of the predetermined mask opposing to the source lightly doped region and a transmittance of a region of the predetermined mask opposing to the source heavily doped region are successively increased in that order; the transmittance of the region of the predetermined mask opposing to the channel region, a transmittance of a region of the predetermined mask opposing to the drain lightly doped region and a transmittance of a region of the predetermined mask opposing to the drain heavily doped region are successively increased in that order.

3 . The manufacturing method according to claim 1 , wherein simultaneously forming a polysilicon layer and a photoresist layer comprises: forming a polysilicon on a surface of the buffer layer, forming a photoresist material on a surface of the polysilicon by spin coating, using a predetermined mask to perform an exposure on the photoresist material, developing the photoresist material after exposure, remaining the polysilicon and the photoresist material in the region where the polysilicon layer and the photoresist layer are formed and removing the polysilicon and the photoresist material in the other location,
wherein a transmittance of a region of the predetermined mask opposing to the channel region, a transmittance of a region of the predetermined mask opposing to the source lightly doped region and a transmittance of a region of the predetermined mask opposing to the source heavily doped region are successively decreased in that order; the transmittance of the region of the predetermined mask opposing to the channel region, a transmittance of a region of the predetermined mask opposing to the drain lightly doped region and a transmittance of a region of the predetermined mask opposing to the drain heavily doped region are successively decreased in that order.

4 . The manufacturing method according to claim 2 , wherein the formation of the polysilicon is that forming an amorphous silicon layer on the surface of the buffer layer by a sputtering process and then recrystallizing the amorphous silicon layer by an annealing process.

5 . The manufacturing method according to claim 2 , wherein the predetermined mask is a halftone mask or a grayscale mask.

6 . The manufacturing method according to claim 4 , wherein the predetermined mask is a halftone mask or a grayscale mask.

7 . The manufacturing method according to claim 3 , wherein the formation of the polysilicon is that forming an amorphous silicon layer on the surface of the buffer layer by a sputtering process and then recrystallizing the amorphous silicon layer by an annealing process.

8 . The manufacturing method according to claim 3 , wherein the predetermined mask is a halftone mask or a grayscale mask.

9 . The manufacturing method according to claim 7 , wherein the predetermined mask is a halftone mask or a grayscale mask.

10 . The manufacturing method according to claim 5 , wherein a material of the photoresist layer is a positive photoresist material.

11 . The manufacturing method according to claim 6 , wherein a material of the photoresist layer is a positive photoresist material.

12 . The manufacturing method according to claim 8 , wherein a material of the photoresist layer is a negative photoresist material.

13 . The manufacturing method according to claim 9 , wherein a material of the photoresist layer is a negative photoresist material.

14 . The manufacturing method according to claim 1 , wherein a thickness of the photoresist layer on the source heavily doped region and a thickness of the photoresist layer on the drain heavily doped region are the same, a thickness of the photoresist layer on the source lightly doped region and a thickness of the photoresist layer on the drain lightly doped region are the same.

Assignees

• Shenzhen China Star Optoelect

Inventors

• Chen Gui
• Xue Jingfeng
• Zhang Xin

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P76/2041

  Photolithographic processes · CPC title

• H10P76/204

  of organic photoresist masks · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title