Method for forming group iii/v conformal layers on silicon substrates

Patent metadata

Field	Value
Publication number	US-2016343811-A1
Application number	US-201615185749-A
Country	US
Kind code	A1
Filing date	Jun 17, 2016
Priority date	Mar 30, 2012
Publication date	Nov 24, 2016
Grant date	—

Abstract

A method for forming a conformal group III/V layer on a silicon substrate and the resulting substrate with the group III/V layers formed thereon. The method includes removing the native oxide from the substrate, positioning a substrate within a processing chamber, heating the substrate to a first temperature, cooling the substrate to a second temperature, flowing a group III precursor into the processing chamber, maintaining the second temperature while flowing a group III precursor and a group V precursor into the processing chamber until a conformal layer is formed, heating the processing chamber to an annealing temperature, while stopping the flow of the group III precursor, and cooling the processing chamber to the second temperature. Deposition of the III/V layer may be made selective through the use of halide gas etching which preferentially etches dielectric regions.

First claim

1 . A method of forming a layer, comprising:
positioning a substrate in a processing chamber, the substrate comprising an exposed surface; delivering a first group III precursor to the exposed surface of the substrate while depositing a nucleation layer on the exposed surface; and delivering a second group III precursor and a group V precursor while depositing a group III/V layer.

2 . The method of claim 1 , wherein the group V precursor continues to flow after the flow of the second group III precursor is stopped.

3 . The method of claim 1 , wherein the chamber is heated to from about 550° C. to about 650° C. prior to delivering the first group III precursor.

4 . The method of claim 3 , wherein the chamber is cooled to about 250° C. to about 400° C. prior to stopping the group V precursor flow.

5 . The method of claim 1 , wherein the first group III precursor and the second group III precursor are aluminum, gallium, indium or combinations thereof.

6 . The method of claim 1 , wherein the group III/V layer is a ternary layer.

7 . The method of claim 1 , wherein the group III/V layer is less than 50 nm thick.

8 . A method of forming a layer, comprising:
cleaning an exposed surface of a substrate; depositing a group III nucleation layer over the exposed surface at a first temperature; depositing a binary or ternary group III/V layer on the group III nucleation layer at a second temperature; and annealing the binary or ternary group III/V layer.

9 . The method of claim 8 , wherein the group III nucleation layer is deposited to a thickness of between 10 nm and 30 nm.

10 . The method of claim 8 , wherein the second temperature is higher than the first temperature.

11 . The method of claim 8 , further comprising depositing one or more additional binary or ternary group III/V layers and annealing the additional binary or ternary group III/V layers.

12 . The method of claim 11 , wherein at least one of the additional binary or ternary group III/V layers comprises a group III element or a group V element which is different from the previous binary or ternary group III/V layer.

13 . The method of claim 12 , wherein the second temperature is maintained during the deposition of the additional binary or ternary group III/V layers.

14 . The method of claim 8 , wherein the binary or ternary group III/V layer is annealed at a temperature between about 400° C. and about 600° C.

15 . A device, comprising:
a silicon substrate comprising:
a first surface; and
a second surface disposed opposite the first surface;
a group III nucleation layer disposed on the first surface of the silicon substrate; and a group III/V buffer layer on top of the group III nucleation layer.

16 . The device of claim 15 , further comprising one or more binary or ternary group III/V layers formed on the group III/V buffer layer.

17 . The device of claim 16 , wherein the group III/V buffer layer or the one or more binary or ternary group III/V layers are composed of the same group III or the same group V element as the buffer layer.

18 . The device of claim 15 , wherein the group III nucleation layer and group III/V buffer layer comprise aluminum, gallium, indium or combinations thereof.

19 . The device of claim 15 , wherein the group III/V buffer layer comprises phosphorus, arsenic or combinations thereof.

20 . The device of claim 15 , wherein the group III/V buffer layer is a binary layer.

Assignees

• Applied Materials Inc

Inventors

• Bao Xinyu
• Sanchez Errol Antonio C
• Carlson David K
• Ye Zhiyuan

Classifications

• H10P14/3822

  Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing · CPC title

• H10P14/3414

  being group IIIA-VIA materials · CPC title

• H10P14/3214

  being Group IIIA-VA semiconductors · CPC title

• H10P14/2905 Primary

  Silicon, silicon germanium or germanium · CPC title

• H10P14/24 Primary

  using chemical vapour deposition [CVD] · CPC title