Contact structure and extension formation for iii-v nfet

Patent metadata

Field	Value
Publication number	US-2016343585-A1
Application number	US-201514930258-A
Country	US
Kind code	A1
Filing date	Nov 2, 2015
Priority date	May 21, 2015
Publication date	Nov 24, 2016
Grant date	—

Abstract

FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions.

First claim

1 . A method comprising:
obtaining a semiconductor structure including a semiconductor substrate and a plurality of columns extending from the semiconductor substrate, the columns being separated by a plurality of recesses, each of the columns including a III-V base and a III-V fin structure, the III-V fin structure being positioned on the III-V base; epitaxially growing a silicon-containing layer on the semiconductor substrate and within the recesses such that a portion of the silicon-containing layer adjoins the III-V fin structures, wherein epitaxially growing the silicon-containing layer includes epitaxially growing a first, p-type silicon layer on the semiconductor substrate and a second silicon layer on the first, p-type silicon layer; causing diffusion of silicon from the silicon-containing layer into the III-V fin structures to form n-type junctions, and forming n-type source/drain regions from the second silicon layer.

2 . The method of claim 1 , wherein the III-V base of each column includes a semi-isolating III-V layer adjoining one of the III-V fin structures.

3 . (canceled)

4 . The method of claim 1 , wherein the step of forming n-type source/drain regions from the silicon-containing layer includes implanting dopant ions within the second silicon layer and annealing the second silicon layer to recrystallize the second silicon layer following ion implantation.

5 . The method of claim 4 , wherein each column further includes a gate structure adjoining one of the III-V fin structures.

6 . The method of claim 4 , wherein the step of obtaining the semiconductor structure includes:
obtaining the semiconductor substrate, the semiconductor substrate comprising monocrystalline silicon; forming a first III-V layer on the semiconductor substrate; forming a semi-isolating layer of III-V material on the first III-V layer; forming III-V fin structures on the semi-isolating layer of III-V material, and forming the plurality of recesses through the first III-V layer, the semi-isolating layer of III-V material, and the III-V fin structures.

7 . The method of claim 6 , further including the step of forming a hard mask on the III-V fin structures prior to forming the plurality of recesses.

8 . The method of claim 7 , wherein the step of forming the hard mask includes forming gate structures on the III-V fin structures and spacers on the gate structures.

9 . The method of claim 2 , further including forming local isolation regions on the semi-isolating layer of III-V material.

10 . (canceled)

11 . The method of claim 1 , wherein the III-V fin structures comprise arsenic, and further wherein the step of causing diffusion of silicon from the silicon-containing layer into the III-V fin structures includes annealing the semiconductor structure such that arsenic from the III-V fin structures is diffused into the second silicon layer.

12 . The method of claim 6 , wherein forming the first III-V layer on the semiconductor substrate further includes growing, in order, gallium arsenide, indium phosphide and indium gallium arsenide on the semiconductor substrate.

13 . The method of claim 6 , wherein forming III-V fin structures on the semi-isolating layer of III-V material further includes growing a blanket III-V layer onto the semi-isolating layer and then removing selected portions of the blanket layer to obtain the fin structures.

14 . The method of claim 13 , wherein the semi-isolating layer is formed from InAlAs and the III-V fin structures are formed from In 0.53 Ga 0.47 As.

15 . The method of claim 1 , wherein the semiconductor substrate is a silicon substrate.

16 . The method of claim 13 , wherein the second silicon layer is epitaxially grown as an undoped layer.

Assignees

• IBM

Inventors

• Basker Veeraraghavan S
• Reznicek Alexander

Classifications

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P95/904

  of Group III-V semiconductors · CPC title

• H10P95/408

  of Group III-V semiconductors, e.g. to render them semi-insulating · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P32/174

  being Group III-V material · CPC title