Memory Cell

Patent metadata

Field	Value
Publication number	US-2016343437-A1
Application number	US-201615225642-A
Country	US
Kind code	A1
Filing date	Aug 1, 2016
Priority date	Jan 10, 2014
Publication date	Nov 24, 2016
Grant date	—

Abstract

Cell layouts for a memory cell, such as for ternary content addressable memory (TCAM), are disclosed. Some cell layouts include a well strap structure. A cell layout may include a p-doped well, an n-doped well, and a p-doped well sequentially along a layout. Another cell layout may include a p-doped well, an n-doped well, a p-doped well, and an n-doped well sequentially along a layout. A well strap structure may be in a p-doped well or an n-doped well. Various metallization layers having a mesh may be used with a memory cell layout. In some disclosed examples, a first metallization layer may have one, two, or four ground traces, and a second metallization layer may have two ground traces. These various ground traces may be electrically coupled together to form a mesh.

First claim

What is claimed is:

1 . A cell structure comprising:
a content addressable memory structure located at least partially within a substrate; a well strap structure having an active area in the substrate; a first metallization layer over the substrate and comprising a first ground trace and a well strap trace each extending in a first direction, the active area of the well strap structure being electrically coupled to the well strap trace; and a second metallization layer over the substrate and comprising a second ground trace and a third ground trace each extending in a second direction, the first direction intersecting the second direction, the second ground trace and the third ground trace being electrically coupled to the first ground trace.

2 . The cell structure of claim 1 , wherein the first ground trace comprises a first portion with a longitudinal axis and a second portion extending from the first portion.

3 . The cell structure of claim 2 , wherein the second portion extends away from the first portion at a right angle.

4 . The cell structure of claim 1 , wherein the second metallization layer further comprises a word line trace adjacent to the third ground trace and a match line trace adjacent to the word line trace.

5 . The cell structure of claim 4 , wherein a distance between the match line trace and the word line trace is larger than a distance between the work line trace and the third ground trace.

6 . The cell structure of claim 1 , wherein the first ground trace is rectangular in shape.

7 . A cell structure comprising:
a first group of transistors, a first set of the first group of transistors forming a first latch, a second set of the first group of transistors forming a second latch, wherein each transistor within the first group of transistors has a FinFET structure; a second group of transistors forming a cascaded device electrically connected to the first latch and the second latch, wherein each transistor within the second group of transistors has a multiple FinFET structure; a first metallization layer overlying the first group of transistors and the second group of transistors, the first metallization layer comprising:
a first ground trace extending over the first group of transistors;
a first power trace extending over the first group of transistors; and
a search line extending over the first group of transistors; and
a second metallization layer overlying the first metallization layer, the second metallization layer comprising a second ground trace and a third ground trace, wherein the first ground trace is electrically connected with both the second ground trace and the third ground trace.

8 . The cell structure of claim 7 , further comprising a well strap structure located adjacent to an edge of the cell structure.

9 . The cell structure of claim 8 , wherein the well strap structure is electrically connected to a fourth ground trace in the first metallization layer.

10 . The cell structure of claim 8 , wherein the well strap structure is electrically connected to a second power trace in the first metallization layer.

11 . The cell structure of claim 7 , further comprising a word line trace adjacent to the second ground trace in the second metallization layer.

12 . The cell structure of claim 11 , further comprising a match line trace adjacent to the word line trace in the second metallization layer.

13 . The cell structure of claim 12 , wherein the match line trace is separated from the word line trace by a first distance and wherein the word line trace is separated from the second ground trace by a second distance less than the first distance.

14 . The cell structure of claim 7 , wherein the first ground trace has a “T” shape.

15 . A cell structure comprising:
a first cell comprising:
a first data latch;
a second data latch; and
a cascaded device connected to both the first data latch and the second data latch;
a second cell adjacent to the first cell; and a well strap structure shared between the first cell and the second cell, wherein the well strap structure comprises an active area electrically coupled to a power node or a ground node.

16 . The cell structure of claim 15 , wherein the first data latch comprises six devices, the second data latch comprises six device, and the cascaded device comprises four devices.

17 . The cell structure of claim 15 , wherein the cascaded device comprises:
a first search gate transistor, the first search gate transistor comprising a first source region electrically connected to a ground; a second search gate transistor, the second search gate transistor comprising a second source region electrically connected to the ground; a first data gate transistor connected to the first search gate transistor, the first data gate transistor comprising a first drain region connected to a match line; and a second data gate transistor connected to the second search gate transistor, the second data gate transistor comprising a second drain region connected to the match line.

18 . The cell structure of claim 17 , wherein the first search gate transistor is connected to a search line, the second search gate transistor is connected to a complementary search line, the first data gate transistor is connected to the first data latch, and the second data gate transistor is connected to the second data latch.

19 . The cell structure of claim 15 , wherein the cascaded device comprises:
a first search gate transistor, the first search gate transistor comprising a first drain region electrically connected to a match line; a second search gate transistor, the second search gate transistor comprising a second drain region electrically connected to the match line; a first data gate transistor connected to the first search gate transistor, the first data gate transistor comprising a first source region connected to a ground; and a second data gate transistor connected to the second search gate transistor, the second data gate transistor comprising a second source region connected to the ground.

20 . The cell structure of claim 19 , wherein the first search gate transistor is connected to a search line, the second search gate transistor is connected to a complementary search line, the first data gate transistor is connected to the first data latch, and the second data gate transistor is connected to the second data latch.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liaw Jhon Jhy

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H01L27/0886

  Electricity · mapped topic