Method of stress relief in anti-reflective coated cap wafers for wafer level packaged infrared focal plane arrays

US2016340179A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016340179-A1
Application numberUS-201615227181-A
CountryUS
Kind codeA1
Filing dateAug 3, 2016
Priority dateAug 23, 2012
Publication dateNov 24, 2016
Grant date

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  1. Title

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  5. First independent claim

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Abstract

Official abstract text for this publication.

Methods for reducing wafer bow induced by an anti-reflective coating of a cap wafer are provided. The method may utilize a shadow mask having at least one opening therein that is positioned opposite recessed regions in a cap wafer. The method may further include depositing at least one layer of an anti-reflective coating material through the shadow mask onto a planar side of a cap wafer to provide a discontinuous coating on the planar side.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method of reducing wafer bow induced by an anti-reflective coating on a cap wafer, the method comprising: providing the cap wafer having a planar side and an opposing cavity side, the cavity side including at least one recessed region and a dividing region on either side of the at least one recessed region; and depositing a layer of an anti-reflective coating material onto the planar side of the cap wafer to provide a discontinuous coating on the planar side such that the discontinuous coating is dimensioned and configured to partially overlap the dividing region. 2 . The method of claim 1 , wherein the discontinuous coating is dimensioned and configured such that a wafer bow induced by the anti-reflective coating is less than 30 microns. 3 . The method of claim 2 , wherein the wafer bow is less than 20 microns. 4 . The method of claim 1 , wherein the discontinuous coating is dimensioned and configured to extend beyond the at least one recessed region. 5 . The method of claim 1 , wherein the discontinuous coating is dimensioned and configured to correspond to saw streets on the cap wafer. 6 . The method of claim 1 , further comprising depositing a layer of an anti-reflective coating material in the recessed regions on the cavity side of the cap wafer to provide a discontinuous coating on the cavity side. 7 . The method of claim 6 , wherein the discontinuous coating on the planar side is dimensioned and configured such that a wafer bow induced by the anti-reflective coating is less than 30 microns. 8 . The method of claim 6 , wherein the discontinuous coating on the planar side is dimensioned and configured such that a wafer bow induced by the anti-reflective coating is in balance with a wafer bow induced by the anti-reflective coating on the cavity side. 9 . The method of claim 6 , further comprising providing a device wafer onto which at least one MEMS device is formed. 10 . The method of claim 9 , further comprising: positioning the cap wafer over the device wafer such that the cavity side of the cap wafer is facing the at least one MEMS device; aligning the cap wafer to the device wafer such that the at least one recessed region is positioned over the at least one MEMS device; and bonding the cap wafer to the device wafer to create bonding structures. 11 . The method of claim 10 , further comprising inspecting the bonding structures through inspection regions provided by the discontinuous coating on the planar side of the cap wafer. 12 . The method of claim 11 , wherein the inspection is performed using a charge-coupled device (CCD). 13 . A method of reducing wafer bow induced by an anti-reflective coating on a cap wafer, the method comprising: providing the cap wafer having a planar side and an opposing cavity side; depositing a first discontinuous layer of anti-reflective coating material onto the cavity side of the cap wafer; and depositing a second discontinuous layer of anti-reflective coating material onto the planar side of the cap wafer such that the second discontinuous coating is dimensioned differently than the first discontinuous coating. 14 . A cap wafer, comprising: a planar side and an opposing cavity side; a first discontinuous layer of anti-reflective coating material disposed onto the cavity side; and a second discontinuous layer of anti-reflective coating material disposed onto the planar side such that the second discontinuous layer of anti-reflective coating material is dimensioned differently than the first discontinuous coating. 15 . The cap wafer of claim 14 , wherein the cavity side of the cap wafer includes a plurality of recessed regions and the first discontinuous layer of anti-reflective coating is disposed in the plurality of recessed regions. 16 . The cap wafer of claim 14 , wherein the dimensions of the second discontinuous layer of anti-reflective coating material are larger than the dimensions of the first discontinuous layer of anti-reflective coating material. 17 . The cap wafer of claim 14 , wherein the second discontinuous layer of anti-reflective coating corresponds to saw streets on the cap wafer such that the dimensions of the anti-reflective coating material extend to the saw streets.

Assignees

Inventors

Classifications

  • for reducing stress inside of the package structure · CPC title

  • Bolometers · CPC title

  • for controlling the passage of optical signals through the package · CPC title

  • Bonding a wafer on the substrate, i.e. where the cap consists of another wafer · CPC title

  • Special surface effect · CPC title

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What does patent US2016340179A1 cover?
Methods for reducing wafer bow induced by an anti-reflective coating of a cap wafer are provided. The method may utilize a shadow mask having at least one opening therein that is positioned opposite recessed regions in a cap wafer. The method may further include depositing at least one layer of an anti-reflective coating material through the shadow mask onto a planar side of a cap wafer to prov…
Who is the assignee on this patent?
Raytheon Co
What technology area does this patent fall under?
Primary CPC classification B81C1/00325. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Thu Nov 24 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).