New dual-gate trench igbt with buried floating p-type shield

Patent metadata

Field	Value
Publication number	US-2016336394-A1
Application number	US-201514712599-A
Country	US
Kind code	A1
Filing date	May 14, 2015
Priority date	May 14, 2015
Publication date	Nov 17, 2016
Grant date	—

Abstract

A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.

First claim

1 . An insulated gate bipolar transistor (IGBT) device supported in a semiconductor substrate wherein:
the semiconductor substrate comprising an epitaxial layer of a first conductivity type supported on a bottom layer of a second conductivity type electrically contacting a collector electrode disposed on a bottom surface of the semiconductor substrate; the IGBT device further comprises a body region of the second conductivity type disposed near a top surface of the semiconductor substrate encompassing a source region of the first conductivity type below a top surface of the semiconductor substrate; the epitaxial layer further includes an upper heavily doped layer having a higher dopant concentration of the first conductivity type below the body region; the IGBT device further comprises a first trench gate and a second trench gate disposed on two opposite sides of the body region and a planar gate disposed on the top surface of the semiconductor substrate extending laterally over the first trench gate to the body region; and. a vertical gate oxide covering and encapsulating the planar gate.

2 . The IGBT device of claim 1 wherein:
the second trench gate is electrically connected to a gate electrode.

3 . The IGBT device of claim 1 further comprising:
a vertical gate oxide having a thickness of approximately 1000 Angstroms covering and encapsulating the planar gate.

4 . The IGBT device of claim 1 further comprising:
a floating buried ring type disposed below a trench bottom surface of a second trench;
the planar gate extends substantially perpendicularly to the first and second trench gates; and
the floating buried ring extending laterally as a stripe aligned with the first and second trench gates.

5 . A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising:
preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.

6 . The method of claim 5 further comprising:
forming a vertical gate oxide covering and encapsulating the planar gate.

7 . The method of claim 5 further comprising:
electrically connecting the first trench gate to a gate electrode.

8 . The method of claim 5 further comprising:
electrically connecting the planar gate to a gate electrode.

9 . The method of claim 5 further comprising:
electrically connecting the second trench gate to a source electrode.

10 . The method of claim 5 further comprising:
electrically connecting the second trench gate to a gate electrode.

11 . The method of claim 5 further comprising:
forming a vertical gate oxide having a thickness of approximately 1000 Angstroms covering and encapsulating the planar gate.

12 . The method of claim 5 further comprising:
padding the first trench gate and the second trench gate with a gate insulation layer before filling the trenches with the polysilicon layer.

13 . The method of claim 5 further comprising:
implanting through the second trench to form a floating buried ring below a trench bottom surface of the second trench gate.

14 . The method of claim 5 further comprising:
implanting dopants of the second conductivity type through the second trench to form a floating buried ring below a trench bottom surface of the second trench gate.

Assignees

• Alpha & Omega Semiconductor

Inventors

• Hu Jun
• Bobde Madhur
• Yilmaz Hamza

Classifications

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title

• H10D64/518

  characterised by their lengths or sectional shapes · CPC title

• H10D64/516

  the thicknesses being non-uniform · CPC title

• H10D64/514

  characterised by the insulating layers · CPC title