Thin film transistor device, manufacturing method thereof, and display apparatus

Patent metadata

Field	Value
Publication number	US-2016336359-A1
Application number	US-201515030576-A
Country	US
Kind code	A1
Filing date	Aug 14, 2015
Priority date	Dec 3, 2014
Publication date	Nov 17, 2016
Grant date	—

Abstract

Various embodiments provide a thin film transistor (TFT) device, a manufacturing method of the TFT device, and a display apparatus including the TFT device. An etch stop layer (ESL) material is formed on an active layer on a substrate. An electrical conductive layer material is formed on the ESL material for forming a source electrode and a drain electrode. The electrical conductive layer material is patterned to form a first portion of the source electrode containing a first via-hole through the source electrode, and to form a first portion of the drain electrode containing a second via-hole through the drain electrode. The ESL material is patterned to form an etch stop layer (ESL) pattern including a first ESL via-hole connecting to the first via-hole through the source electrode and including a second ESL via-hole connecting to the second via-hole through the drain electrode.

First claim

1 - 22 . (canceled)

23 . A method for forming a thin-film transistor (TFT) device, comprising:
forming an etch stop layer (ESL) material on an active layer on a substrate; forming an electrical conductive layer material on the ESL material for forming a source electrode and a drain electrode; patterning the electrical conductive layer material to form a first portion of the source electrode containing a first via-hole through the source electrode, and to form a first portion of the drain electrode containing a second via-hole through the drain electrode; and patterning the ESL material to form an etch stop layer (ESL) pattern including a first ESL via-hole connecting to the first via-hole through the source electrode and including a second ESL via-hole connecting to the second via-hole through the drain electrode.

24 . The method according to claim 23 , wherein a mask used for patterning the ESL is one of masks used for patterning the electrical conductive layer material and a passivation layer formed over the source electrode and the drain electrode.

25 . The method according to claim 24 , wherein patterning the electrical conductive layer material and patterning the ESL material include:
forming a first photoresist layer on the electrical conductive layer material; exposing the first photoresist layer using the mask for patterning the electrical conductive layer material; developing the exposed first photoresist layer to form a first photoresist pattern; etching the electrical conductive layer material to form the first portion of the source electrode containing the first via-hole through the source electrode, and to form the first portion of the drain electrode containing the second via-hole through the drain electrode; forming the passivation layer material over the substrate having the source electrode and the drain electrode; and patterning the passivation layer material to form a passivation layer.

26 . The method according to claim 25 , further including:
forming a second photoresist layer on the passivation layer material; exposing the second photoresist layer using another mask for patterning the passivation layer material; developing the second photoresist layer to form a second photoresist pattern; etching the passivation layer material to form the passivation layer between the first portion of the source electrode and the first portion of the drain electrode to expose the first via-hole through the source electrode, and to expose the second via-hole through the drain electrode; and patterning the ESL material to form the ESL pattern including the first ESL via-hole through the ESL material connecting to the first via-hole through the source electrode and including the second ESL via-hole through the ESL material connecting to the second via-hole through the drain electrode using the mask.

27 . The method according to claim 25 , wherein the electrical conductive layer material is etched by a wet etching.

28 . The method according to claim 26 , wherein the passivation layer material and the ESL material are etched by a dry etching.

29 . The method according to claim 24 , wherein patterning the electrical conductive layer material and patterning the ESL material include:
using a single patterning process for: patterning the electrical conductive layer material to form the first portion of the source electrode containing the first via-hole through the source electrode, and to form the first portion of the drain electrode containing the second via-hole through the drain electrode; and patterning the ESL material to form the ESL pattern including the first ESL via-hole connecting to the first via-hole through the source electrode and including the second ESL via-hole connecting to the second via-hole through the drain electrode.

30 . The method according to claim 29 , wherein using the single patterning process for patterning the electrical conductive layer material and for patterning the ESL material includes:
forming a third photoresist layer on the electrical conductive layer material; using the mask for patterning the electrical conductive layer material to expose the third photoresist layer, the third photoresist layer being developed to form a third photoresist pattern; etching the electrical conductive layer material using the third photoresist pattern to form the first portion of the source electrode containing the first via-hole through the source electrode, and to form the first portion of the drain electrode containing the second via-hole through the drain electrode; and then, etching the ESL material using the third photoresist pattern to form the first ESL via-hole connecting to the first via-hole through the source electrode and to form the second ESL via-hole connecting to the second ESL via-hole through the drain electrode.

31 . The method according to claim 29 , wherein:
the electrical conductive layer material is etched by a wet etching, and the ESL material is etched by a dry etching.

32 . The method according to claim 23 , after forming the first via-hole through the source electrode and forming the second via-hole through the drain electrode, further including:
using a patterning process to form a transparent conductive layer such that the transparent conductive layer connects the active layer with each of the first portion of the source electrode and the first portion of the drain electrode by having the transparent conductive layer on surfaces of the first via-hole through the source electrode, on surfaces of the second via-hole through the drain electrode, on surfaces of the first ESL via-hole, and on surfaces the second ESL via-hole.

33 . The method according to claim 32 , wherein the transparent conductive layer includes a common electrode or a pixel electrode.

34 . The method according to claim 29 , after the single patterning process, further including:
forming a passivation layer material, and patterning the passivation layer material to form a passivation layer, wherein the passivation layer material is etched to remove portions corresponding to the first via-hole through the source electrode and the second via-hole through the drain electrode and to remove portions of the passivation layer material on the first portion of the source electrode and on the first portion of the drain electrode.

35 . The method according to claim 34 , wherein the passivation layer is formed between the first portion of the source electrode and the first portion of the drain electrode, exposing the first via-hole through the source electrode and exposing the second via-hole through the drain electrode.

36 . The method according to claim 34 , after forming the passivation layer, further including:
using a patterning process to form a transparent conductive layer, such that the transparent conductive layer connects the active layer with each of the first portion of the source electrode and the first portion of the drain electrode by having the transparent conductive layer on surfaces of the first via-hole through the source electrode, on surfaces of the second via-hole through the drain electrode, on surfaces of the first ESL via-hole, and on surfaces the second ESL via-hole.

37 . The method according to claim 36 , wherein the transparent conductive layer includes a common electrode or a pixel electrode.

38 . The method according to claim 23 , before forming the ESL material on the active layer further including:
forming a gate electrode on the substrate, forming a gate insulating layer on the gate electrode,

Assignees

• Boe Technology Group Co Ltd
• Chongqing Boe Optoelectronics Tech Co Ltd

Inventors

• Wang Wu
• Qiu Haijun
• Shang Fei
• Wang Guolei

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P76/2041

  Photolithographic processes · CPC title

• H10P50/282

  of inorganic materials · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10D84/01 Primary

  Manufacture or treatment · CPC title