Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2016336320-A1
Application number	US-201514714231-A
Country	US
Kind code	A1
Filing date	May 15, 2015
Priority date	May 15, 2015
Publication date	Nov 17, 2016
Grant date	—

Abstract

A semiconductor device includes first and second Fin FETs and a separation plug made of an insulating material and disposed between the first and second Fin FETs. The first Fin FET includes a first fin structure extending in a first direction, a first gate dielectric formed over the first fin structure and a first gate electrode formed over the first gate dielectric and extending in a second direction perpendicular to the first direction. The second Fin FET includes a second fin structure, a second gate dielectric formed over the second fin structure and a second gate electrode formed over the first gate dielectric and extending in the second direction. When viewed from above, an end shape the separation plug has a concave curved shape, while an end of the first gate electrode abutting the separation plug has a convex curved shape.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a first Fin FET including a first fin structure extending in a first direction, a first gate dielectric formed over the first fin structure and a first gate electrode formed over the first gate dielectric and extending in a second direction perpendicular to the first direction; a second Fin FET including a second fin structure, a second gate dielectric formed over the second fin structure and a second gate electrode formed over the first gate dielectric and extending in the second direction; and a separation plug made of an insulating material and disposed between the first Fin FET and the second FinFET, wherein when viewed from above, an end shape the separation plug has a concave curved shape, while an end of the first gate electrode abutting the separation plug has a convex curved shape.

2 . The semiconductor device of claim 1 , wherein in a cross section along the second direction and across the first gate electrode, the separation plug has a tapered shape having a top width smaller than a bottom width.

3 . The semiconductor device of claim 2 , further comprising an isolation insulating layer disposed at least between the first fin structure and the second fin structure, wherein:
the separation plug is disposed over the isolation insulating layer, and a taper angle of the separation plug at a bottom of the separation plug measured with respect to a surface of the isolation insulating layer is 90 degrees or more.

4 . The semiconductor device of claim 1 , wherein:
the first gate electrode includes a first metal gate material, and the second gate electrode includes a second metal gate material.

5 . The semiconductor device of claim 4 , wherein:
the first gate electrode further includes one or more layers of first work function adjusting metals disposed between the first gate dielectric layer and the first metal gate material, and the second gate electrode further includes one or more layers of second work function adjusting metals disposed between the second gate dielectric layer and the second metal gate material.

6 . The semiconductor device of claim 1 , wherein the first Fin FET and the second Fin FET have a same channel type.

7 . The semiconductor device of claim 1 , wherein a channel type of the first Fin FET is different from a channel type of the second Fin FET.

8 . The semiconductor device of claim 1 , wherein two or more first fin structures are included in the first Fin FET.

9 . A method for manufacturing a semiconductor device, comprising:
forming a dummy electrode structure including a dummy gate electrode layer and side-wall insulating layer disposed at both main sides of the dummy gate electrode layer, and interlayer dielectric layers disposed at both main sides of the dummy electrode layer; removing part of the dummy gate electrode layer so that a first space and a second space are formed between the side-wall insulating layers, the first electrode space and the second electrode space being separated by a pillar that is a remaining part of the dummy gate electrode layer; forming a first gate structure and a second gate structure in the first electrode space and the second electrode space, respectively; removing the pillar so that an opening is formed between the first gate structure and the second gate structure; and forming a separation plug by filling the opening with an insulating material.

10 . The method of claim 9 , wherein when viewed from above, an end shape the separation plug has a concave curved shape, while an end of the first gate structure abutting the separation plug has a convex curved shape.

11 . The method of claim 9 , wherein in a cross section along the second direction and across the first gate electrode, the separation plug has a tapered shape having a top width smaller than a bottom width.

12 . The method of claim 11 , further comprising forming an isolation insulating layer at least between the first fin structure and the second fin structure, wherein:
the separation plug is disposed over the isolation insulating layer, and a taper angle of the separation plug at a bottom of the separation plug measured with respect to a surface of the isolation insulating layer is 90 degrees or more.

13 . The method of claim 9 , wherein the removing part of the dummy gate electrode layer comprises:
forming a mask pattern on a region corresponding to the pillar; and etching the dummy gate electrode layer by using the mask pattern.

14 . The method of claim 13 , wherein the mask pattern is made at least one of silicon oxide, silicon oxynitride and silicon nitride.

15 . The method of claim 13 , further comprising reducing a width of the mask pattern,
wherein etching the dummy gate electrode layer is performed by using the mask pattern with the reduced width.

16 . The method of claim 9 , wherein the forming a separation plug comprises:
forming the insulating material over the first and second gate structures and in the opening; and removing a portion of the insulating material, thereby forming the separation plug of the insulating material filled in the opening.

17 . The method of claim 9 , wherein the forming dummy electrode structure comprises:
forming a fin structure; forming an isolation layer so that a lower part of the fin structure is embedded in the isolation layer; forming a first dielectric layer over the fin structure; and forming the dummy electrode layer over the first dielectric layer.

18 . The method of claim 9 , wherein the dummy gate electrode layer includes poly silicon.

19 . The method of claim 17 , wherein the forming the first gate structure and the second gate structure comprises:
forming a second dielectric layer; forming one or more layers of first work function adjusting metals for the first gate structure over the second dielectric layer; forming one or more layers of second work function adjusting metals for the second gate structure over the second dielectric layer; forming a first metal gate material over the one or more layers of first work function adjusting metals; and forming a second gate material over the one or more layers of second work function adjusting metals.

20 . A semiconductor device, comprising:
an FET including a first gate dielectric layer and a metal gate electrode; and a separation plug made of an insulating material and disposed adjacent to the FET, wherein when viewed from above, an end shape the separation plug has a concave curved shape, while an end of the metal gate electrode abutting the separation plug has a convex curved shape.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Chih-Han

Classifications

• H10P50/268

  of silicon-containing layers · CPC title

• H10D30/795

  being in lateral device isolation regions, e.g. STI · CPC title

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title