Dual fin integration for electron and hole mobility enhancement

Patent metadata

Field	Value
Publication number	US-2016336236-A1
Application number	US-201615219894-A
Country	US
Kind code	A1
Filing date	Jul 26, 2016
Priority date	Feb 24, 2015
Publication date	Nov 17, 2016
Grant date	—

Abstract

A technique for forming a semiconductor device is provided. Sacrificial mandrels are formed over a hardmask layer on a semiconductor layer. Spacers are formed on sidewalls of the sacrificial mandrels. The sacrificial mandrels are removed to leave the spacers. A masking process leaves exposed a first set of spacers with a second set protected. In response to the masking process, a first fin etch process forms a first set of fins in the semiconductor layer via first set of spacers. The first set of fins has a vertical sidewall profile. Another masking process leaves exposed the second set of spacers with the first set of spacers and the first set of fins protected. In response to the other masking process, a second fin etch process forms a second set of fins in semiconductor layer using the second set of spacers. The second set of fins has a trapezoidal sidewall profile.

First claim

What is claimed is:

1 . A method of forming a semiconductor device, the method comprising:
forming a plurality of sacrificial mandrels over a hardmask layer, the hardmask layer disposed over a semiconductor layer; forming a plurality of spacers on sidewalls of the plurality of sacrificial mandrels; removing the plurality of sacrificial mandrels to leave the plurality of spacers; performing a masking process to leave exposed a first set of the plurality of spacers with a second set of the plurality of spacers protected; in response to the masking process, performing a first fin etch process to form a first set of fins in the semiconductor layer using the first set of the plurality of spacers, wherein the first set of fins has a vertical sidewall profile; performing another masking process to leave exposed the second set of the plurality of spacers with the first set of the plurality of spacers and the first set of fins protected; in response to the another masking process, performing a second fin etch process to form a second set of fins in the semiconductor layer using the second set of the plurality of spacers, wherein the second set of fins has a trapezoidal sidewall profile.

2 . The method of claim 1 , wherein during the masking process a first mask covers the second set of the plurality of spacers.

3 . The method of claim 2 , wherein the first mask is an oxide.

4 . The method of claim 1 , wherein during the another masking process a second mask covers the first set of the plurality of spacers.

5 . The method of claim 4 , wherein the second mask is an oxide.

6 . The method of claim 1 , wherein the plurality of spacers include at least one of an oxide and a nitride.

7 . The method of claim 1 , wherein the semiconductor layer comprises at least one of silicon and germanium.

8 . The method of claim 1 , wherein the first set of fins comprises positive channel field effect transistors (PFET) devices.

9 . The method of claim 1 , wherein the second set of fins comprises negative channel field effect transistors (NFET) devices.

10 . The method of claim 1 , wherein a gate electrode is formed over the first set of fins and the second set of fins.

11 . The method of claim 1 , wherein a base width of the second set of fins is at least twice a length of a top width of the second set of fins.

12 . The method of claim 1 , wherein a height of the second set of fins is about equal to a height of the first set of fins.

13 . The method of claim 1 , wherein an integrated circuit includes the first set of fins and the second set of fins.

14 . The method of claim 13 , wherein an individual microprocessor includes the integrated circuit having the first set of fins and the second set of fins, such that the first set of fins comprises PFET devices and the second set of fins comprises NFET devices.

Assignees

• IBM

Inventors

• Chen Chia-Yu
• Liu Zuoguang
• Wang Miaomiao
• Yamashita Tenko

Classifications

• H10P76/408

  characterised by their sizes, orientations, dispositions, behaviours or shapes · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/694

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

• H10P50/693

  characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title