Devices and methods to receive input at a first device and present output in response on a second device different from the first device
US-9213659-B2 · Dec 15, 2015 · US
High-speed data transmission using pcie protocol
US2016335209A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016335209-A1 |
| Application number | US-201514708921-A |
| Country | US |
| Kind code | A1 |
| Filing date | May 11, 2015 |
| Priority date | May 11, 2015 |
| Publication date | Nov 17, 2016 |
| Grant date | — |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
Embodiments generally relate to data transmission in a computing system. The present technology discloses techniques that that can enable a high-bandwidth and low-latency data transmission using PCIe (Peripheral Component Interconnect Express) technology. According to some embodiments, by utilizing the PCIe protocol, the present technology can achieve high-speed data transmission for intra-rack network trafficking.
First claim
Opening claim text (preview).
What is claimed is: 1 . A method, comprising: receiving, at a computer Input/Output (I/O) expansion backplane communicatively coupled to a plurality of nodes, data generated by a first node of the plurality of nodes; determining a destination of the data based at least in part on information associated with the data; and transmitting the data to a second node associated with the determined destination of the data, wherein the computer expansion backplane is coupled to a pl…
Assignees
Inventors
Classifications
- G06F13/36Primary
Physics · mapped topic
Physics · mapped topic
- G06F13/385Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US2016335209A1 cover?
- Embodiments generally relate to data transmission in a computing system. The present technology discloses techniques that that can enable a high-bandwidth and low-latency data transmission using PCIe (Peripheral Component Interconnect Express) technology. According to some embodiments, by utilizing the PCIe protocol, the present technology can achieve high-speed data transmission for intra-rack…
- Who is the assignee on this patent?
- Quanta Comp Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F13/36. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Thu Nov 17 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).