Method and apparatus for spectrum spreading of a pulse-density modulated waveform

Patent metadata

Field	Value
Publication number	US-2016330053-A1
Application number	US-201615096973-A
Country	US
Kind code	A1
Filing date	Apr 12, 2016
Priority date	Apr 11, 2014
Publication date	Nov 10, 2016
Grant date	—

Abstract

Methods and systems are provided for spreading spectral density of pulse streams during digital to analog conversion. An example spreading circuit may comprise an accumulator circuit, a bit generator circuit, a comparator circuit, and an inverter circuit. The accumulator circuit may be operable to receive a signal to be spread and generate an output based on the signal to be spread and at least one other input. The bit generator circuit may be operable to input into the accumulator circuit zero-sum sequences. The comparator circuit may be operable to provide a stream of pulses based on the output of the accumulator circuit. The inverter circuit may be operable to invert output of the comparator circuit, wherein output of the inverter circuit is input into the accumulator circuit.

First claim

1 - 18 . (canceled)

19 . A system comprising:
an accumulator circuit operable to receive a signal to be spread and generate an output based on the signal to be spread and at least one other input; a bit generator circuit operable to input into the accumulator circuit zero-sum sequences; a comparator circuit operable to provide a stream of pulses based on the output of the accumulator circuit; and an inverter circuit operable to invert output of the comparator circuit, wherein output of the inverter circuit is input into the accumulator circuit.

20 . The system of claim 19 , wherein the number of pulses in the stream of pulses output from the comparator circuit is equal to the number of pulses in the signal to be spread.

21 . The system of claim 19 , comprising a delay circuit for delaying inputting of the output of the accumulator circuit into the comparator circuit.

22 . The system of claim 21 , wherein the delay circuit is synchronized to the output of the bit generator circuit.

23 . The system of claim 21 , wherein the delay circuit and the bit generator circuit are synchronized to the signal to be spread.

24 . The system of claim 19 , wherein the bit generator circuit comprises a zero-sum sequence register.

25 . The system of claim 19 , wherein the zero-sum sequences comprise a sequence of 1s and −1s, each zero-sum sequence having an equal number of 1s and −1s.

26 . The system of claim 19 , comprising a random number generator coupled to the bit generator circuit.

27 . The system of claim 26 , wherein the random number generator is a linear feedback shift register (LFSR).

28 . The system of claim 26 , wherein the delay circuit and the bit generator circuit are synchronized to the signal to be spread and the random number generator is synchronized to a clock running at one fourth the frequency of the signal to be spread.

29 . The system of claim 19 , wherein the zero-sum sequences comprise four bit long sequences.

30 . The system of claim 19 , wherein the comparator circuit is operable to output a 1 if the output of the delay circuit is greater than zero and to output a zero if the output of the delay circuit is not greater than zero.

31 . The system of claim 19 , wherein the inverter circuit is operable to output a zero if the input to the inverter circuit is zero and is to output a −1 if the input to the inverter circuit is 1.

32 . The system of claim 19 , wherein the output of the accumulator circuit is a 3-bit signed value.

33 . A method comprising:
in an electronic device that comprises a pulse width modulation (PDM) digital-to-analog converter (DAC), generating a spread spectrum representation of a PDM DAC bit stream, the generating comprising:
generating a subsequent sum based on summing of a first bit of a PDM DAC bit stream with a first bit of a zero-sum sequence;
determine a next subsequent sum by summing the subsequent sum with:
a zero if the subsequent sum is not greater than zero and a negative one if the subsequent sum is greater than zero,
a next bit of the PDM DAC bit stream, and
a next bit of the zero-sum sequence; and

repeat the summing for each bit of the PDM DAC bit stream to provide a spread spectrum representation of the PDM DAC bit stream in which each bit of the spread spectrum representation is either a one or a zero depending upon whether the subsequent sum is greater than zero.

Assignees

• Entropic Communications Llc

Inventors

• Petrovic Branislav
• Alelyunas Carl Harry

Classifications

• H04L27/04

  Modulator circuits; Transmitter circuits · CPC title

• H03M1/822

  using pulse width modulation · CPC title

• H04L27/103 Primary

  Chirp modulation (for spread spectrum techniques H04B1/69) · CPC title

• H04L25/4902 Primary

  Pulse width modulation; Pulse position modulation · CPC title

• H04B1/7172

  Pulse shape (in general H04L25/03834) · CPC title