Dual frequency fmcw lidar and method
US-2018210068-A1 · Jul 26, 2018 · US
US10148473B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10148473-B2 |
| Application number | US-201815860016-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 2, 2018 |
| Priority date | Apr 11, 2014 |
| Publication date | Dec 4, 2018 |
| Grant date | Dec 4, 2018 |
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Methods and systems are provided for spreading spectral density of digital-to-analog conversion output signals. A spreading circuit may spread a digital-to-analog converter (DAC) output signal over a particular frequency spectrum, with the spreading circuit receiving the DAC output signal; generating a plurality of internal control signals; and generating based on the DAC output signal and the one or more internal control signal a corresponding spread output signal. The Internal control signals may comprise at least a first control signal, generated based on sequences meeting at least one particular criterion, a second control signal, generated based on a feedback corresponding to an intermediate output generated within the spreading circuit. The spreading circuit may generate the first control signal based on zero-sum sequences. The spreading circuit may generate a stream of pulses based on the intermediate output, and may generate the feedback signal based on the stream of pulses.
Opening claim text (preview).
What is claimed is: 1. A system comprising: a digital-to-analog converter (DAC) circuit that generates an output signal; and a spreading circuit that spreads the DAC output signal over a particular frequency spectrum, wherein the spreading circuit: receives the DAC output signal; generates a plurality of internal control signals, wherein; the spreading circuit generates at least a first control signal based on sequences meeting at least one particular criterion; and the spreading circuit generates a second control signal based on a feedback corresponding to an intermediate output generated within the spreading circuit; and generates based on the DAC output signal and the plurality of internal control signals, a corresponding spread output signal. 2. The system of claim 1 , wherein generating the second control signal comprises applying an adjustment to the intermediate output. 3. The system of claim 1 , wherein the spreading circuit sets the second control signal based on applying of inversion to the intermediate output. 4. The system of claim 1 , wherein the spreading circuit generates a stream of pulses based on the intermediate output; and generates the feedback signal based on the stream of pulses. 5. The system of claim 4 , wherein the spreading circuit sets a number of pulses in the stream of pulses to equal to a number of pulses in the DAC output signal. 6. The system of claim 4 , wherein the spreading circuit sets the second control signal based on comparing of a value corresponding to the intermediate output with a pre-defined value. 7. The system of claim 1 , wherein generating the second control signal comprises applying a delay. 8. The system of claim 7 , wherein applying the delay is synchronized to the generating of the first control signal. 9. The system of claim 8 , wherein applying the delay and generating the first control signal are synchronized to the DAC output signal. 10. The system of claim 1 , wherein the spreading circuit generates the first control signal based on zero-sum sequences. 11. The system of claim 10 , wherein the zero-sum sequences comprise sequences of 1s and −1s, each zero-sum sequence having an equal number of 1s and −1s. 12. The system of claim 10 , wherein the zero-sum sequences comprise four bit long sequences. 13. The system of claim 1 , wherein the spreading circuit generates the first control signal based on randomly generated number. 14. The system of claim 13 , wherein the spreading circuit generates the randomly generated number based on linear feedback shifting. 15. The system of claim 13 , wherein generating the first control signal is synchronized to the DAC output signal and generating the randomly number is synchronized to a clock set based on a frequency of the DAC output signal.
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