Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2016322495-A1
Application number	US-201615138840-A
Country	US
Kind code	A1
Filing date	Apr 26, 2016
Priority date	Apr 28, 2015
Publication date	Nov 3, 2016
Grant date	—

Abstract

A semiconductor device includes an active pattern protruding from a substrate and extending in a first direction, first and second gate electrodes intersecting the active pattern in a second direction intersecting the first direction, and a source/drain region disposed on the active pattern between the first and second gate electrodes. The source/drain region includes a first part adjacent to an uppermost surface of the active pattern and provided at a level lower than the uppermost surface of the active pattern, and a second part disposed under the first part so as to be in contact with the first part. A width of the first part along the first direction decreases in a direction away from the substrate, and a width of the second part along the first direction increases in a direction away from the substrate.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a substrate; an active pattern protruding from the substrate and extending in a first direction; first and second gate electrodes intersecting the active pattern in a second direction intersecting the first direction, the first and second gate electrodes spaced apart from each other along the first direction; and a source/drain region disposed on the active pattern between the first and second gate electrodes, wherein the source/drain region comprises: a first part adjacent to an uppermost surface of the active pattern, the first part provided at a level lower than the uppermost surface of the active pattern; and a second part being in contact with the first part, the second part disposed under the first part, wherein a width of the first part along the first direction decreases in a direction away from the substrate, and wherein a width of the second part along the first direction increases in a direction away from the substrate.

2 . The semiconductor device of claim 1 , wherein each of the first part and the second part has a maximum thickness in a direction perpendicular to a top surface of the substrate, and
wherein the maximum thickness of the first part ranges from about 5% to about 15% of the sum of the maximum thicknesses of the first and second parts.

3 . The semiconductor device of claim 2 , wherein the maximum thickness of the first part ranges from about 2 nm to about 8 nm.

4 . The semiconductor device of claim 1 , wherein an angle between a sidewall of the first part and the uppermost surface of the active pattern is an acute angle at a contact point between the sidewall of the first part and the uppermost surface of the active pattern.

5 . The semiconductor device of claim 4 , wherein the angle between the sidewall of the first part and the uppermost surface of the active pattern ranges from about 40 degrees to about 60 degrees.

6 . The semiconductor device of claim 1 , wherein the second part has a rounded bottom surface having a U-shape.

7 . The semiconductor device of claim 1 , wherein the source/drain region comprises silicon-germanium (SiGe) doped with boron.

8 . The semiconductor device of claim 1 , wherein the active pattern comprises: a boron-doped region comprising boron, and
wherein the boron-doped region is adjacent to the uppermost surface of the active pattern and is in contact with the first part.

9 . The semiconductor device of claim 8 , wherein a boron concentration of the boron-doped region ranges from about 10 14 atoms/cm 3 to about 10 15 atoms/cm 3 .

10 . The semiconductor device of claim 8 , wherein each of the boron-doped region and the first part has a maximum thickness in a direction perpendicular to a top surface of the substrate, and
wherein the maximum thickness of the first part is equal to or greater than the maximum thickness of the boron-doped region.

11 . The semiconductor device of claim 8 , wherein the boron-doped region comprises a plurality of boron-doped regions, and
wherein one of the boron-doped regions is located between the source/drain region and the first gate electrode, and another of the boron-doped regions is located between the source/drain region and the second gate electrode.

12 . The semiconductor device of claim 8 , wherein a width of the boron doping region increases in a direction away from the substrate.

13 . A semiconductor device comprising:
a substrate; an active pattern protruding from the substrate, the active pattern extending in a first direction, and the active pattern having a recess region recessed from an uppermost surface of the active pattern; first and second gate electrodes intersecting the active pattern in a second direction intersecting the first direction, the first and second gate electrodes spaced apart from each other with the recess region interposed therebetween; and a source/drain region filling the recess region, wherein the recess region comprises: a bottom surface; a pair of first inner walls connected to the uppermost surface of the active pattern, wherein a width between the pair of first inner walls along the first direction increases in a direction away from the uppermost surface of the active pattern; and a pair of second inner walls connected between the bottom surface and the pair of first inner walls, wherein a width between the pair of second inner walls along the first direction decreases in a direction away from the uppermost surface of the active pattern.

14 . The semiconductor device of claim 13 , wherein the bottom surface has a rounded shape.

15 . The semiconductor device of claim 13 , wherein an angle between each of the first inner walls of the recess region and the uppermost surface of the active pattern is an acute angle at a contact point between each of the first inner walls of the recess region and the uppermost surface of the active pattern.

16 . The semiconductor device of claim 15 , wherein the angle between each of the first inner walls of the recess region and the uppermost surface of the active pattern ranges from about 40 degrees to about 60 degrees.

17 . The semiconductor device of claim 13 , wherein the source/drain region comprises:
a first source/drain layer conformally covering the first inner walls, the second inner walls and the bottom surface of the recess region; and a second source/drain layer disposed on the first source/drain layer to fill the recess region, wherein the source/drain region comprises silicon-germanium (SiGe) doped with boron, and wherein a composition ratio of germanium (Ge) contained in the second source/drain layer is greater than a composition ratio of Ge contained in the first source/drain layer.

18 . The semiconductor device of claim 17 , wherein the first source/drain layer has a U-shape when viewed from a cross-sectional view.

19 . The semiconductor device of claim 13 , wherein the active pattern comprises: a pair of boron-doped regions,
wherein one of the pair of boron-doped regions is provided between the first gate electrode and one of the pair of first inner walls, and wherein the other of the pair of the boron-doped regions is provided between the second gate electrode and the other of the pair of first inner walls.

20 . The semiconductor device of claim 19 , wherein each of the boron-doped regions has a width in the first direction, and
wherein the width of each of the boron-doped regions increases in a direction away from the substrate.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Moon Kanghun
• Kim Jinbum
• Lee Kwan Heum
• Lee Choeun
• Jung Sujin
• Xu Yang

Classifications

• H10D30/6211

  having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D62/832

  being Group IV materials comprising two or more elements, e.g. SiGe · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title