Multichip integration with through silicon via (tsv) die embedded in package

Patent metadata

Field	Value
Publication number	US-2016322344-A1
Application number	US-201615208502-A
Country	US
Kind code	A1
Filing date	Jul 12, 2016
Priority date	May 13, 2013
Publication date	Nov 3, 2016
Grant date	—

Abstract

Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with three-dimensional (3D) integration of multiple dies, as well as corresponding fabrication methods and systems incorporating such 3D IC package assemblies. A bumpless build-up layer (BBUL) package substrate may be formed on a first die, such as a microprocessor die. Laser radiation may be used to form an opening in a die backside film to expose TSV pads on the back side of the first die. A second die, such as a memory die stack, may be coupled to the first die by die interconnects formed between corresponding TSVs of the first and second dies. Underfill material may be applied to fill some or all of any remaining gap between the first and second dies, and/or an encapsulant may be applied over the second die and/or package substrate. Other embodiments may be described and/or claimed.

First claim

1 - 10 . (canceled)

11 . A method comprising:
providing a first die having a side with an electrical routing feature, a first through silicon via (TSV) coupled with the electrical routing feature, and an adhesive layer coupled to the side with an opening in the adhesive layer; and coupling a second die with the side of the first die such that the adhesive layer is disposed between the first die and the second die, wherein the second die has a second TSV coupled with the first TSV by a conductive path disposed through the opening in the adhesive layer.

12 . The method of claim 11 , further comprising coupling the adhesive layer to the side of the first die.

13 . The method of claim 12 , wherein coupling the adhesive layer to the second side of the first die includes placing a portion of the adhesive layer on the electrical routing feature, the method further comprising:
placing the first die and the adhesive layer onto a sacrificial panel, with the adhesive layer disposed between the first die and the sacrificial panel; and removing the sacrificial panel from the adhesive layer after forming the one or more build-up layers on the first side of the die, wherein forming the opening in the adhesive layer includes removing the portion of the adhesive layer after removing the sacrificial panel to expose the electrical routing feature.

14 . The method of claim 11 , further comprising forming the opening in the adhesive layer.

15 . The method of claim 14 , wherein forming the opening in the adhesive layer includes exposing a portion of the adhesive layer to laser radiation.

16 . The method of claim 15 , wherein exposing the portion of the adhesive layer to laser radiation is performed by a laser projection patterning tool.

17 . The method of claim 15 , wherein removing the portion of the adhesive layer further includes scanning the portion of the adhesive layer with an ultraviolet (UV) laser.

18 . The method of claim 11 , further comprising applying a molding material over the second die such that the second die is embedded in the molding material.

19 . The method of claim 11 , further comprising applying an underfill material between the first die and the second die.

20 . The method of claim 11 , wherein the side is a first side, and wherein the first die further includes a second side opposite the first side, the second side having one or more transistors.

Assignees

• Intel Corp

Inventors

• Raorane Digvijay A
• Li Yonggang
• Manepalli Rahul N
• Gonzalez Javier Soto

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title