Schottky barrier diode and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2016308071-A1
Application number	US-201514690209-A
Country	US
Kind code	A1
Filing date	Apr 17, 2015
Priority date	Apr 17, 2015
Publication date	Oct 20, 2016
Grant date	—

Abstract

A method of manufacturing a Schottky barrier diode is provided, which includes: providing a semiconductor substrate including a first well region of a first conductivity type in the semiconductor substrate; forming a surface-doped layer having a dopant of a second conductivity type opposite to the first conductivity type in the first well region; forming a dielectric layer in contact with the surface-doped layer; performing a thermal treatment on the surface-doped layer to move the dopant of the surface-doped layer in the dielectric layer; removing the dielectric layer to expose the first well region; and forming a silicide layer in contact with the exposed first well region. A Schottky barrier diode is also provided.

First claim

1 . (canceled)

2 . (canceled)

3 . (canceled)

4 . (canceled)

5 . (canceled)

6 . (canceled)

7 . (canceled)

8 . A method of manufacturing a Schottky barrier diode, the method comprising:
providing a semiconductor substrate comprising a first well region of a first conductivity type in the semiconductor substrate; forming a surface-doped layer having a dopant of a second conductivity type opposite to the first conductivity type in the first well region; forming a dielectric layer in contact with the surface-doped layer after forming the surface-doped layer; performing a thermal treatment on the surface-doped layer to remove the dopant from the surface-doped layer and to move the dopant into the dielectric layer; removing the dielectric layer having the dopant to expose the first well region; and forming a silicide layer in contact with the exposed first well region; forming a silicon nitride-containing layer over the surface-doped layer after forming the surface-doped layer and before forming the dielectric layer; and removing the silicon nitride-containing layer.

9 . The method of claim 8 , wherein performing the thermal treatment on the surface-doped layer is comprised in forming the dielectric layer.

10 . The method of claim 8 , further comprising forming a second well region of the second conductivity type in the first well region after forming the dielectric layer, and the second well region is configured to surround the silicide layer.

11 . The method of claim 10 , wherein forming the second well region of the second conductivity type is before removing the dielectric layer.

12 . The method of claim 10 , wherein performing the thermal treatment on the surface-doped layer is comprised in forming the second well region.

13 . (canceled)

14 . The method of claim 8 , wherein the dielectric layer excludes silicon nitride.

15 . The method of claim 8 , wherein the dielectric layer includes silicon oxide.

16 . The method of claim 8 , wherein the thermal treatment is greater than or equal to 400° C.

17 . A method of manufacturing a Schottky barrier diode, the method comprising:
providing a semiconductor substrate comprising a first well region of a first conductivity type in the semiconductor substrate and an isolation region in the first well region to define a diode area of the first well region and a contact area of the first well region separated from each other by the isolation region; forming a surface-doped layer having a dopant of a second conductivity type opposite to the first conductivity type in the diode area of the first well region; forming a dielectric layer over the first well region and in contact with the surface-doped layer after forming the surface-doped layer; performing a thermal treatment on the surface-doped layer to remove the dopant from the surface-doped layer and to move the dopant into the dielectric layer; patterning the dielectric layer having the dopant to expose the diode area of the first well region, wherein patterning the dielectric layer further comprises maintaining the dielectric layer remaining over the isolation region; and forming a silicide layer in contact with the exposed diode area of the first well region.

18 . The method of claim 17 , wherein patterning the dielectric layer further comprises exposing the contact area of the first well region, and the method further comprises forming a heavily doped layer of the first conductivity type in the contact area of the first well region.

19 . (canceled)

20 . The method of claim 17 , further comprising forming a second well region of the second conductivity type in the diode area of the first well region after forming the dielectric layer, and the second well region is configured to surround the silicide layer.

21 . The method of claim 8 , wherein the thermal treatment is lower than or equal to 1200° C.

22 . The method of claim 8 , wherein the semiconductor substrate further comprises a deep well region of the first conductivity type beneath the first well region.

23 . The method of claim 8 , wherein forming the dielectric layer in contact with the surface-doped layer and performing the thermal treatment on the surface-doped layer are conducted by a thermal oxidation process.

24 . The method of claim 10 , wherein performing the thermal treatment on the surface-doped layer and forming the second well region of the second conductivity type in the first well region are conducted by implanting a dopant of the second conductivity type in the first well region and performing an annealing process.

25 . The method of claim 17 , wherein forming the dielectric layer over the first well region and in contact with the surface-doped layer and performing the thermal treatment on the surface-doped layer are conducted by a thermal oxidation process.

26 . The method of claim 20 , wherein performing the thermal treatment on the surface-doped layer and forming the second well region of the second conductivity type in the diode area of the first well region are conducted by implanting a dopant of the second conductivity type into the diode area of the first well region and performing an annealing process.

27 . The method of claim 17 , wherein forming the surface-doped layer having the dopant of the second conductivity type opposite to the first conductivity type in the diode area of the first well region further comprises forming the surface-doped layer having the dopant of the second conductivity type opposite to the first conductivity type in the contact area of the first well region.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Meng-Han
• Chou Chien-Chih
• Hsiung Chih-Wen
• Thei Kong-Beng

Classifications

• H10P32/20

  Diffusion for doping of insulating layers · CPC title

• H10P32/1406

  by ion implantation · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P32/141

  the applied layer comprising oxides only · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title