Array Substrate, Driving Method Thereof and Display Device

Patent metadata

Field	Value
Publication number	US-2016300541-A1
Application number	US-201615086537-A
Country	US
Kind code	A1
Filing date	Mar 31, 2016
Priority date	Apr 10, 2015
Publication date	Oct 13, 2016
Grant date	—

Abstract

The present invention provides an array substrate, a driving method thereof, and a display device. The array substrate comprises a plurality of gate lines and a plurality of data lines, and the plurality of gate lines cross with the plurality of data lines to define a plurality of pixel units. Each of the pixel units comprises a first pixel electrode, a second pixel electrode and a floating electrode which are insulated from each other, and the floating electrode is provided in a layer different from that in which the first pixel electrode and the second pixel electrode are provided. The first pixel electrode and the second pixel electrode are capable of forming a plane electric field therebetween, and the floating electrode and both the first pixel electrode and the second pixel electrode are capable of forming a fringe electric field therebetween.

First claim

What is claimed is:

1 . An array substrate, comprising a plurality of gate lines and a plurality of data lines, the plurality of gate lines crossing with the plurality of data lines to define a plurality of pixel units, wherein, each of the pixel units comprises a first pixel electrode, a second pixel electrode and a floating electrode which are insulated from each other, the floating electrode is provided in a layer different from that in which the first pixel electrode and the second pixel electrode are provided, the first pixel electrode and the second pixel electrode are capable of forming a plane electric field therebetween, and the floating electrode and both the first pixel electrode and the second pixel electrode are capable of forming a fringe electric field therebetween.

2 . The array substrate according to claim 1 , wherein, the first pixel electrode and the second pixel electrode are provided in a same layer, the first pixel electrode comprises a plurality of first sub-electrodes which are parallel to each other, provided with a same interval therebetween and of strip shape, the second pixel electrode comprises a plurality of second sub-electrodes which are parallel to each other, provided with a same interval therebetween and of strip shape, and the first sub-electrodes and the second sub-electrodes are parallel to each other, arranged alternately with each other and provided with a same interval therebetween.

3 . The array substrate according to claim 2 , wherein, each of the pixel units further comprises a first transistor and a second transistor, and the data lines comprise a first data line and a second data line; and
both a gate of the first transistor and a gate of the second transistor are connected to a corresponding gate line, a first electrode of the first transistor is connected to the first data line, a second electrode of the first transistor is connected to the first pixel electrode, a first electrode of the second transistor is connected to the second data line, and a second electrode of the second transistor is connected to the second pixel electrode.

4 . The array substrate according to claim 2 , wherein, each of the pixel units further comprises a first transistor and a second transistor, the data lines comprise a first data line and a second data line, and the gate lines comprise a first gate line and a second gate line; and
a gate of the first transistor is connected to the first gate line, a first electrode of the first transistor is connected to the first data line, a second electrode of the first transistor is connected to the first pixel electrode, a gate of the second transistor is connected to the second gate line, a first electrode of the second transistor is connected to the second data line, and a second electrode of the second transistor is connected to the second pixel electrode.

5 . The array substrate according to claim 3 , wherein, the floating electrode is provided above or under both the first pixel electrode and the second pixel electrode, and an insulating layer is provided between the floating electrode and both the first pixel electrode and the second pixel electrode.

6 . The array substrate according to claim 5 , wherein, the floating electrode is of plate shape, and both the first pixel electrode and the second pixel electrode are provided opposite to the floating electrode.

7 . The array substrate according to claim 6 , wherein, the floating electrodes in the pixel units are connected to each other, and are input with a same signal.

8 . The array substrate according to claim 5 , wherein, the floating electrode comprises a plurality of third sub-electrodes which are parallel to each other, provided with a same interval therebetween and of strip shape, the third sub-electrodes are parallel to both the first sub-electrodes and the second sub-electrodes, and each of the third sub-electrodes corresponds to an interval region between the first sub-electrode and the second sub-electrode which are adjacent to said each of the third sub-electrodes.

9 . The array substrate according to claim 8 , wherein, the floating electrodes in the pixel units are connected to each other, and are input with a same signal.

10 . The array substrate according to claim 4 , wherein, the floating electrode is provided above or under both the first pixel electrode and the second pixel electrode, and an insulating layer is provided between the floating electrode and both the first pixel electrode and the second pixel electrode.

11 . The array substrate according to claim 10 , wherein, the floating electrode is of plate shape, and both the first pixel electrode and the second pixel electrode are provided opposite to the floating electrode.

12 . The array substrate according to claim 11 , wherein, the floating electrodes in the pixel units are connected to each other, and are input with a same signal.

13 . The array substrate according to claim 10 , wherein, the floating electrode comprises a plurality of third sub-electrodes which are parallel to each other, provided with a same interval therebetween and of strip shape, the third sub-electrodes are parallel to both the first sub-electrodes and the second sub-electrodes, and each of the third sub-electrodes corresponds to an interval region between the first sub-electrode and the second sub-electrode which are adjacent to said each of the third sub-electrodes.

14 . The array substrate according to claim 13 , wherein, the floating electrodes in the pixel units are connected to each other, and are input with a same signal.

15 . A driving method of the array substrate according to claim 1 , comprising steps of:
when the array substrate is caused to display information, forming a plane electric field between the first pixel electrode and the second pixel electrode; and forming a fringe electric field between the floating electrode and both the first pixel electrode and the second pixel electrode.

16 . The driving method according to claim 15 , wherein,
each of the pixel units further comprises a first transistor and a second transistor, and the data lines comprise a first data line and a second data line; and both a gate of the first transistor and a gate of the second transistor are connected to a corresponding gate line, a first electrode of the first transistor is connected to the first data line, a second electrode of the first transistor is connected to the first pixel electrode, a first electrode of the second transistor is connected to the second data line, and a second electrode of the second transistor is connected to the second pixel electrode; or each of the pixel units further comprises a first transistor and a second transistor, the data lines comprise a first data line and a second data line, and the gate lines comprise a first gate line and a second gate line; and a gate of the first transistor is connected to the first gate line, a first electrode of the first transistor is connected to the first data line, a second electrode of the first transistor is connected to the first pixel electrode, a gate of the second transistor is connected to the second gate line, a first electrode of the second transistor is connected to the second data line, and a second electrode of the second transistor is connected to the second pixel electrode; the driving method specifically comprises steps of: when the array substrate is caused to display information, turning on the first transistor and the second transistor in each of the pixel units at the same time, inputting a first data signal to the first pixel electro

Assignees

• Boe Technology Group Co Ltd
• Hefei Boe Optoelectronics Tech

Inventors

• Cheng Mengde
• Wang Lisen
• Wang Sheng
• Park Kuhyun

Classifications

• G09G2320/0271

  Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping · CPC title

• G09G3/3648 Primary

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G02F2001/134372

  Physics · mapped topic

• G02F1/134363 Primary

  for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS] · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title