Semiconductor device

Patent metadata

Field	Value
Publication number	US-2016294403-A1
Application number	US-201615181877-A
Country	US
Kind code	A1
Filing date	Jun 14, 2016
Priority date	Dec 13, 2013
Publication date	Oct 6, 2016
Grant date	—

Abstract

A semiconductor device according to an aspect of the invention relates to an AD converter that converts a signal level of an analog signal into a digital value by using a comparator, and determines an amount of adjustment of an offset voltage of the comparator based on an offset determination result of the comparator obtained immediately after a least significant bit (LSB) of a digital value output as a conversion result is converted.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a sample-and-hold circuit that samples an input signal, outputs differential voltages to a first comparison line and to a second comparison line; a comparator that outputs an output value according to a voltage difference between the first comparison line and the second comparison line; a digital-to-analog conversion circuit that changes the differential voltages of the first comparison line and the second comparison line according to the output value; a successive approximation control circuit that controls the sample-and-hold circuit, the comparator, and the digital-to-analog conversion circuit according to a preset successive approximation sequence, and outputs a plurality of output bits as a conversion result of the input voltage; and a switch circuit that is provided between the first comparison line and the second comparison line, and that is switched by the successive approximation control circuit, wherein, when the conversion result is acquired, the successive approximation control circuit switches the switch circuit into a conductive state, and outputs control signal to adjust an input offset voltage of the comparator according to the output bits while the switch circuit is in the conductive state, and wherein the comparator changes the input offset voltage according to the control signal.

2 . The semiconductor device according to claim 1 , further comprising:
an offset control circuit that receives the control signal from the successive approximation control circuit and outputs an offset control value to the comparator to change the input offset voltage, wherein the comparator includes:
a pre-amplifier that amplifies the voltage difference between the first comparison line and the second comparison line, and outputs a first intermediate output voltage and a second intermediate output voltage,
a latch circuit that determines a logic level of the output value according to the first intermediate output voltage and the second intermediate output voltage,
a first offset adjustment capacitor connected to a first intermediate voltage line through which the first intermediate output voltage is transmitted from the pre-amplifier to the latch circuit, and
a second offset adjustment capacitor connected to a second intermediate voltage line through which the second intermediate output voltage is transmitted from the pre-amplifier to the latch circuit,
wherein a capacitance ratio between the first offset adjustment capacitor and the second offset adjustment capacitor changes according to the offset control value.

3 . The semiconductor device according to claim 2 , wherein the control signal controls the input offset voltage of the comparator to increase or decrease.

4 . The semiconductor device according to claim 2 , wherein the offset control circuit updates the offset control value after the output bits are generated.

5 . The semiconductor device according to claim 2 , wherein the offset control circuit updates the offset control value after a preset number of cycles of generating the output bits.

6 . The semiconductor device according to claim 5 , wherein the offset control circuit changes the number of cycles after the offset control value is updated.

7 . The semiconductor device according to claim 5 , wherein the offset control circuit determines the control value according to a ratio between a number of positive determinations and a number of negative determinations of the preset number of cycles.

8 . A semiconductor device comprising:
a comparator that outputs a digital value according to a voltage difference between a first comparison line and a second comparison line; and a switch circuit connected between the first comparison line and the second comparison line, wherein the comparator includes:
a first transistor having a gate connected to the first comparison line, and
a second transistor having a gate connected to the second comparison line,
wherein the switch circuit is disposed adjacent to both the first transistor and the second transistor, wherein the first comparison line includes:
a first main line that extends over the switch circuit and extends along the first transistor and the second transistor, and
a first branch line that branches from the first main line to the gate of the first transistor, and
wherein the second comparison line includes:
a second main line that extends over the switch circuit and extends along the first transistor and the second transistor, and
a second branch line that branches from the second main line to the gate of the first transistor.

9 . The semiconductor device according to claim 8 ,
wherein the first branch line and the second branch line are disposed in a layer different from a layer in which the first main line and the second main line are formed, and the first branch line and the second branch line have substantially the same length.

10 . The semiconductor device according to claim 8 , further comprising:
a plurality of shield lines disposed to sandwich the first main line and the second main line.

11 . The semiconductor device according to claim 10 , wherein a switch control line connected to the switch circuit is disposed in outside of the shield lines on a side of the switch circuit away from the comparator.

12 . The semiconductor device according to claim 11 , wherein the switch control line is formed in a wiring layer different from a wiring layer in which the first main line and the second main line are formed.

13 . The semiconductor device according to claim 11 ,
wherein the comparator includes a pair of offset adjustment capacitors that adjust input offset voltages of the comparator, and wherein the offset adjustment capacitors are connected to the comparator by capacitor connecting lines that are orthogonal to the switch control line, and are formed in a wiring layer different from a wiring layer in which the switch control line is formed.

14 . The semiconductor device according to claim 8 , wherein the first main line and the second main line sandwich a central portion of the switch circuit.

15 . The semiconductor device according to claim 8 , wherein the first main line and the second main line sandwich a central portion of a gate of a switch transistor that constitutes the switch circuit.

16 . The semiconductor device according to claim 8 , wherein a distance from the switch circuit to the first transistor is substantially the same as a distance from the switch circuit to the second transistor.

17 . The semiconductor device according to claim 8 , wherein a number of contacts that connect the main line of the first main line to the switch circuit is the same as a number of contacts that connect the second main line to the switch circuit.

18 . The semiconductor device according to claim 8 , wherein a number of regions of the switch circuit to which the first main line is connected is the same as a number of regions of the switch circuit to which the second main line is connected.

19 . The semiconductor device according to claim 8 ,
wherein the comparator includes a pair of offset adjustment capacitors that adjust input offset voltages of the comparator, and wherein the switch circuit is disposed between the first transistor, the second transistor the offset adjustment capacitors.

20 . The semiconductor device according to claim 19 , wherein the offset adjustment capacitors are respectively connected to the first

Assignees

• Renesas Electronics Corp

Inventors

• Kimura Keisuke
• Okuda Yuichi
• Nakane Hideo
• Yamamoto Takaya

Classifications

• H10W20/423

  Shielding layers · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H03M1/0607 Primary

  Offset or drift compensation (removal of offset already present on the analogue input signal H03M1/1295) · CPC title