Optoelectronic Semiconductor Apparatus and Carrier Assembly

Patent metadata

Field	Value
Publication number	US-2016293587-A1
Application number	US-201615183867-A
Country	US
Kind code	A1
Filing date	Jun 16, 2016
Priority date	Sep 14, 2012
Publication date	Oct 6, 2016
Grant date	—

Abstract

A semiconductor apparatus with an optoelectronic device and a further device is disclosed. Embodiments of the invention provide a semiconductor apparatus with an optoelectronic device and a further device, wherein the optoelectronic device and the further device are interconnected to one another in parallel when the semiconductor apparatus is in operation, wherein the optoelectronic device is connected to a first contact and a second contact, the first contact and the second contact being configured to externally contact the semiconductor apparatus, and wherein the further device is connected with at least one further contact of the semiconductor apparatus.

First claim

What is claimed is:

1 . A carrier assembly comprising:
a plurality of device regions arranged adjacent one another in a lateral direction, wherein each device region comprises a first land and a second land on a major face, each land providing electrically contacting for an optoelectronic semiconductor device, wherein each device region comprises on a back opposite the major face a first back contact surface and a second back contact surface, wherein the first back contact surface and the second back contact surface are each electrically conductively connected by a through via with the first land and the second land respectively, and wherein each device region comprises on the major face a first front contact surface electrically conductively connected by a further through via with the first back contact surface.

2 . The carrier assembly according to claim 1 , wherein a current path extending through the carrier assembly between a further front contact surface and the second land of the device regions in each case forms an ESD protective diode.

3 . The carrier assembly according to claim 1 , wherein the carrier assembly is free of a direct front current path between the first land and the first front contact surface, and wherein a current path between the first land and the first front contact surface passes twice through the carrier assembly in a vertical direction extending perpendicularly to the major face.

4 . The carrier assembly according to claim 1 , wherein the carrier assembly comprises a semiconductor material.

5 . The carrier assembly according to claim 1 , wherein each device region comprises a device, the device being integrated into the carrier assembly.

6 . The carrier assembly according to claim 1 , wherein each device is electrically connected with at least one further contact of the carrier assembly, the device being externally electrically contactable via the further contact.

7 . The carrier assembly according to claim 1 , wherein the device region comprises a further contact comprising a further back contact surface.

8 . The carrier assembly according to claim 7 , wherein the first back contact surface and the further back contact surface are adjacent one another without overlap.

9 . The carrier assembly according to claim 1 , wherein the carrier assembly comprises a first region and a second region, the first region and the second region being differently doped from one another with regard to conduction type, wherein the carrier assembly further comprises an insulation layer arranged on the major face of the carrier assembly, and wherein the insulation layer comprises openings in places such that the second land is electrically conductively connected in an opening with the first region and a further front contact surface is electrically conductively connected in a further opening with the second region.

Assignees

• Osram Opto Semiconductors Gmbh

Inventors

• Herrmann Siegfried

Classifications

• H10W72/07251

  characterised by changes in properties of the bump connectors during connecting · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title