Multilayer ceramic electronic device

Patent metadata

Field	Value
Publication number	US-2016293333-A1
Application number	US-201615087275-A
Country	US
Kind code	A1
Filing date	Mar 31, 2016
Priority date	Mar 31, 2015
Publication date	Oct 6, 2016
Grant date	—

Abstract

Provided is a multilayer ceramic electronic device which is capable of preventing decrease of the specific permittivity and of showing less drop of capacitance, even when the dielectric grains constituting the dielectric layers become smaller for thinning of the dielectric layers, wherein Dg/Di≧1 is satisfied, in case that “Di” is an average grain size of the first dielectric grains constituting the dielectric layer in the capacitance region and “Dg” is an average grain size of the second dielectric grains in an exterior area.

First claim

What is claimed is:

1 . A multilayer ceramic electronic device comprising:
a ceramic element body, in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately stacked, and at least a pair of external electrodes which are connected to the internal electrode layers on surfaces of the ceramic element body, wherein a thickness of the dielectric layers is 0.5 μm or less, and Dg/Di≧1 is satisfied, in case that an average grain size of the first dielectric grains constituting the dielectric layer placed between the internal electrode layers along the laminating direction is Di and an average grain size of the second dielectric grains in an exterior area placed outside of the laminating direction of an interior area, in which the internal electrode layers are laminated interposing the dielectric layers along the laminating direction, is Dg.

2 . A multilayer ceramic electronic device comprising:
a ceramic element body, in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately stacked, and at least a pair of external electrodes which are connected to the internal electrode layers on surfaces of the ceramic element body, wherein a thickness of the dielectric layers is 0.5 μm or less, and Dh/Di≧1 is satisfied, in case that an average grain size of the first dielectric grains constituting the dielectric layer placed between the internal electrode layers along the laminating direction is Di and an average grain size of the third dielectric grains constituting a lead-out area placed between the lead-out parts of the internal electrode layers connected to either one of the external electrodes is Dh.

3 . The multilayer ceramic electronic device as set forth in claim 1 , wherein
10% or more of a total number of the first dielectric grains contact the internal electrode layers, placed at the upper and the lower part of the dielectric layers.

4 . The multilayer ceramic electronic device as set forth in claim 2 , wherein
10% or more of a total number of the first dielectric grains contact the internal electrode layers, placed at the upper and the lower part of the dielectric layers.

Assignees

• Tdk Corp

Inventors

• Kaneko Toshihiko
• Murosawa Shogo

Classifications

• H01G4/30 Primary

  Stacked capacitors (H01G4/33 takes precedence) · CPC title

• H01G4/1209

  characterised by the ceramic dielectric material (H01G4/1272, H01G4/1281 take precedence) · CPC title

• H01G4/12

  Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title

• H01G4/232

  electrically connecting two or more layers of a stacked or rolled capacitor · CPC title

• H01G4/248

  the terminals embracing or surrounding the capacitive element, e.g. caps (H01G4/252 takes precedence) · CPC title