Multi-layer ceramic capacitor and method of manufacturing the same
US-2015070817-A1 · Mar 12, 2015 · US
Multilayer ceramic electronic device
US2016284473A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016284473-A1 |
| Application number | US-201615082814-A |
| Country | US |
| Kind code | A1 |
| Filing date | Mar 28, 2016 |
| Priority date | Mar 27, 2015 |
| Publication date | Sep 29, 2016 |
| Grant date | — |
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Abstract
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A multilayer ceramic electronic device comprising: a ceramic element body, in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately stacked, and at least a pair of external electrodes which are connected to the internal electrode layers on surfaces of the ceramic element body; a thickness of the dielectric layers is 0.4 μm or less, a width (W 0 ) of the ceramic element body along a width-direction is 0.59 mm or less, a gap (Wgap) between an outer face of the ceramic element body and an end of the internal electrode layers along width-direction of the ceramic element body is 0.010 to 0.025 mm, and a ratio (Wgap/W 0 ) of the gap with respect to the width is 0.025 or more.
First claim
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What is claimed is: 1 . A multilayer ceramic electronic device comprising: a ceramic element body, in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately stacked, and at least a pair of external electrodes which are connected to the internal electrode layers on surfaces of the ceramic element body, wherein a thickness of the dielectric layers is 0.4 μm or less, a width (W 0 ) of the ceramic element body along a width-direction is 0.59 mm or less, a gap (Wgap) between an outer face of the ceramic element body and an end of the internal electrode layers along width-direction of the ceramic element body is 0.010 to 0.025 mm, and a ratio (Wgap/W 0 ) of the gap with respect to the width is 0.025 or more. 2 . The multilayer ceramic electronic device as set forth in claim 1 , wherein a ratio (te/td) of a thickness (td) of the internal electrode layers with respect to a thickness (te) of the dielectric layers is preferably 1.05 or less. 3 . The multilayer ceramic electronic device as set forth in claim 1 , wherein Dg/Di≧1 is satisfied, in case that an average grain size of the first dielectric grains constituting the dielectric layer placed between the internal electrode layers along the laminating direction is Di and an average grain size of the second dielectric grains in an exterior area placed outside of the laminating direction of an interior area, in which the internal electrode layers are laminated interposing the dielectric layers along the laminating direction, is Dg. 4 . The multilayer ceramic electronic device as set forth in claim 2 , wherein Dg/Di≧1 is satisfied, in case that an average grain size of the first dielectric grains constituting the dielectric layer placed between the internal electrode layers along the laminating direction is Di and an average grain size of the second dielectric grains in an exterior area placed outside of the laminating direction of an interior area, in which the internal electrode layers are laminated interposing the dielectric layers along the laminating direction, is Dg. 5 . The multilayer ceramic electronic device as set forth in claim 1 , wherein Dh/Di≧1 is satisfied, in case that the average grain size of the first dielectric grains constituting the dielectric layers placed between the internal electrode layers along the laminating direction is Di, and an average grain size of the third dielectric grains constituting a lead-out area placed between the lead-out parts of the internal electrode layers connected to either one of the external electrodes is Dh. 6 . The multilayer ceramic electronic device as set forth in claim 2 , wherein Dh/Di≧1 is satisfied, in case that the average grain size of the first dielectric grains constituting the dielectric layers placed between the internal electrode layers along the laminating direction is Di, and an average grain size of the third dielectric grains constituting a lead-out area placed between the lead-out parts of the internal electrode layers connected to either one of the external electrodes is Dh. 7 . The multilayer ceramic electronic device as set forth in claim 3 , wherein Dh/Di≧1 is satisfied, in case that the average grain size of the first dielectric grains constituting the dielectric layers placed between the internal electrode layers along the laminating direction is Di, and an average grain size of the third dielectric grains constituting a lead-out area placed between the lead-out parts of the internal electrode layers connected to either one of the external electrodes is Dh. 8 . The multilayer ceramic electronic device as set forth in claim 4 , wherein Dh/Di≧1 is satisfied, in case that the average grain size of the first dielectric grains constituting the dielectric layers placed between the internal electrode layers along the laminating direction is Di, and an average grain size of the third dielectric grains constituting a lead-out area placed between the lead-out parts of the internal electrode layers connected to either one of the external electrodes is Dh.
Assignees
Inventors
Classifications
Stacked capacitors (H01G4/33 takes precedence) · CPC title
Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title
- H01G4/012Primary
Form of non-self-supporting electrodes · CPC title
characterised by the ceramic dielectric material (H01G4/1272, H01G4/1281 take precedence) · CPC title
based on alkaline earth titanates · CPC title
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- What does patent US2016284473A1 cover?
- A multilayer ceramic electronic device comprising: a ceramic element body, in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately stacked, and at least a pair of external electrodes which are connected to the internal electrode layers on surfaces of the ceramic element body; a thickness of the dielectric layers is 0.4 μm or less, a width (W 0 ) of…
- Who is the assignee on this patent?
- Tdk Corp
- What technology area does this patent fall under?
- Primary CPC classification H01G4/012. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Sep 29 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).