Apparatuses and methods including memory access in cross point memory

Patent metadata

Field	Value
Publication number	US-2016293254-A1
Application number	US-201615180909-A
Country	US
Kind code	A1
Filing date	Jun 13, 2016
Priority date	May 7, 2012
Publication date	Oct 6, 2016
Grant date	—

Abstract

Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.

First claim

What is claimed is:

1 . A method comprising:
applying a first voltage to a first conductive line coupled to memory cells during a first time interval of a memory operation; applying a second voltage to a second conductive line during the first time interval, the second conductive line being coupled to a selected memory cell among the memory cells, wherein an access component in the selected memory cell remains in a nonconductive state during the first time interval; and causing the access component in the selected memory cell to change from the nonconductive state to a conductive state during a second time interval of the memory operation, wherein causing includes applying a third voltage to the first conductive line during the second time interval through a switch coupled to the first conductive line.

2 . The method of claim 1 , wherein the switch includes a phase change material.

3 . The method of claim 1 , wherein applying the first voltage to the first conductive line includes turning on a transistor coupled to the first conductive line to apply the first voltage to the first conductive line through the transistor.

4 . The method of claim 3 , further comprising:
turning off the transistor in the second time interval.

5 . The method of claim 1 , wherein the first and third voltages have opposite polarities.

6 . The method of claim 1 , wherein the second and third voltages have opposite polarities.

7 . The method of claim 1 , wherein the first and second voltages have a same polarity.

8 . The method of claim 1 , wherein the first voltage has a negative value.

9 . The method of claim 1 , wherein applying the first voltage to the first conductive line includes turning on a first transistor coupled to the first conductive line to apply the first voltage to the first conductive line through the transistor, and wherein applying the second voltage to the second conductive line includes turning on a second transistor coupled to the second conductive line to apply the second voltage to the second conductive line through the second transistor.

10 . The method of claim 9 , further comprising:
applying a fourth voltage to the second conductive line during the second time interval through an additional switch coupled to the second conductive line.

11 . The method of claim 10 , further comprising:
turning off the second transistor in the second time interval.

12 . The method of claim 10 , wherein the third and fourth voltages have opposite polarities.

13 . The method of claim 10 , wherein the second and third voltages have a same polarity.

14 . The method of claim 1 , wherein the second voltage has a positive value.

15 . The method of claim 1 , further comprising:
sensing information stored in the selected memory cell after the access component in the selected memory cell is in the conductive state.

16 . The method of claim 1 , further comprising:
storing information into the selected memory cell after the access component in the selected memory cell is in the conductive state.

17 . The method of claim 1 , wherein a voltage difference between the first and third voltages is greater than a threshold voltage of the first switch.

18 . The method of claim 1 , wherein a voltage difference between the first and third voltages is less than a threshold voltage of the selected memory cell.

19 . The method of claim 1 , further comprising applying a fourth voltage to the second conductive line during the second time interval through an additional switch coupled to the second conductive line, wherein applying the first voltage to the first conductive line includes turning on a first transistor coupled to the first conductive line to apply the first voltage to the first conductive line through the transistor, applying the second voltage to the second conductive line includes turning on a second transistor coupled to the second conductive line to apply the second voltage to the second conductive line through the second transistor, and a voltage difference between the second and fourth voltages is greater than a threshold voltage of the additional switch.

20 . The method of claim 1 , further comprising applying a fourth voltage to the second conductive line during the second time interval through an additional switch coupled to the second conductive line, wherein applying the first voltage to the first conductive line includes turning on a first transistor coupled to the first conductive line to apply the first voltage to the first conductive line through the transistor, applying the second voltage to the second conductive line includes turning on a second transistor coupled to the second conductive line to apply the second voltage to the second conductive line through the second transistor, and a voltage difference between the third and fourth voltages is greater than a threshold voltage of the selected memory cell.

Assignees

• Micron Technology Inc

Inventors

• Kau Derchang
• Spadini Gianpaolo

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C13/0023

  Address circuits or decoders · CPC title

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title