Array substrate and manufacturing method thereof, display panel and display device

Patent metadata

Field	Value
Publication number	US-2016291431-A1
Application number	US-201414438644-A
Country	US
Kind code	A1
Filing date	Aug 20, 2014
Priority date	Mar 7, 2014
Publication date	Oct 6, 2016
Grant date	—

Abstract

The present invention provides an array substrate and a manufacturing method thereof, a display panel and a display device. The manufacturing method of an array substrate in the present invention comprises: forming light-shielding layers on the base substrate through a patterning process by using a light-shielding layer-doping multiplexing mask plate; and performing doping of CMOS transistors by using the light-shielding layer-doping multiplexing mask plate. In the invention, two mask plates used in manufacturing the light-shielding layer and the doping process in the prior art are replaced with one light-shielding layer-doping multiplexing mask plate, therefore the number of the mask plates during manufacturing is reduced and the cost is decreased. Meanwhile, providing of the light-shielding layer below the N type transistors in the driving region of the array substrate may prevent light-induced leakage current from being generated in the conductive region.

First claim

1 - 9 . (canceled)

10 . A manufacturing method of an array substrate comprising a step of forming light-shielding layers on a base substrate, and a step of forming first type transistors and second type transistors above the light shielding layers, wherein
the step of forming light-shielding layers on a base substrate comprises: forming a pattern of the light-shielding layers on the base substrate through a patterning process by using a light-shielding layer-doping multiplexing mask plate, wherein the light-shielding layer-doping multiplexing mask plate has a shielding portion corresponding to a conductive region of an active layer of each of the first type transistors in a driving region on the base substrate, and a shielding portion corresponding to a conductive region of an active layer of each of the first type transistors in a display region on the base substrate, the light-shielding layers are formed in positions corresponding to the conductive regions of the active layers of the first type transistors in the driving region and positions corresponding to the conductive regions of the active layers of the first type transistors in the display region, the step of forming first type transistors and second type transistors above the light-shielding layers comprises: performing a first type doping on active layers of the first type transistors and the second type transistors; and performing a second type doping on the second type transistors by shielding the conductive regions of the active layers of the first type transistors using the light-shielding layer-doping multiplexing mask plate.

11 . The manufacturing method of an array substrate of claim 10 , wherein
performing a first type doping on active layers of the first type transistors and the second type transistors comprises: doping N type atoms into the active layers of the first type transistors and the second type transistors to form N type transistors; and doping P type atoms into the active layers of the second type transistors to form P type transistors.

12 . The manufacturing method of an array substrate of claim 10 , wherein
performing a first type doping on active layers of the first type transistors and the second type transistors comprises: doping P type atoms into the active layers of the first type transistors and the second type transistors to form P type transistors; and doping N type atoms into the active layers of the second type transistors to form N type transistors.

13 . The manufacturing method of an array substrate of claim 10 , wherein the step of forming an active layer comprises following steps:
depositing an amorphous silicon thin film by a low pressure chemical vapor deposition method, wherein the amorphous silicon film is crystallized into a polycrystalline silicon film as the active layer at a low temperature; or directly depositing a polycrystalline silicon film as the active layer by a low pressure chemical vapor deposition method.

14 . The manufacturing method of an array substrate of claim 11 , wherein the step of forming an active layer comprises following steps:
depositing an amorphous silicon thin film by a low pressure chemical vapor deposition method, wherein the amorphous silicon film is crystallized into a polycrystalline silicon film as the active layer at a low temperature; or directly depositing a polycrystalline silicon film as the active layer by a low pressure chemical vapor deposition method.

15 . The manufacturing method of an array substrate of claim 12 , wherein the step of forming an active layer comprises following steps:
depositing an amorphous silicon thin film by a low pressure chemical vapor deposition method, wherein the amorphous silicon film is crystallized into a polycrystalline silicon film as the active layer at a low temperature; or directly depositing a polycrystalline silicon film as the active layer by a low pressure chemical vapor deposition method.

16 . An array substrate comprising a base substrate, the base substrate comprises a display region for displaying and a driving region at periphery of the display region, wherein the driving region of the base substrate is provided with first type transistors and second type transistors, and the display region of the base substrate is provided with first type transistors, and wherein
light-shielding layers are provided below conductive regions of active layers of the first type transistors.

17 . The array substrate of claim 16 , wherein
the first type transistors are N type transistors, and the second type transistors are P type transistors; or the first type transistors are P type transistors, and the second type transistors are N type transistors.

18 . The array substrate of claim 14 , wherein the N type transistors are made by performing N type doping on low temperature polycrystalline silicon, and the P type transistors are made by performing P type doping on low temperature polycrystalline silicon.

19 . The array substrate of claim 15 , wherein the N type transistors are made by performing N type doping on low temperature polycrystalline silicon, and the P type transistors are made by performing P type doping on low temperature polycrystalline silicon.

20 . A display panel comprising the array substrate of claim 14 .

21 . A display device comprising the display panel of claim 20 .

Assignees

• Boe Technology Group Co Ltd
• Chengdu Boe Optoelect Tech Co

Inventors

• Hu Like
• Qi Xiaojing

Classifications

• H10P14/3802

  Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P14/3456

  Polycrystalline · CPC title

• H10P14/3454

  Amorphous · CPC title