Display panel and display module

US2016291378A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016291378-A1
Application numberUS-201314382005-A
CountryUS
Kind codeA1
Filing dateNov 6, 2013
Priority dateAug 19, 2013
Publication dateOct 6, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present invention relates to a display panel and a display module, the display panel comprises a display region and a non-display region, and boundaries between the display region and the non-display region comprise at least one arc structure. The technical effects of the present invention are that it is beneficial to design a display module with an arc and narrow frame, which greatly reduces the range of the frame, increases the area that can be displayed, it is more consistent with the natural display contour of the human eye's physiology, with more comfortable, natural and fantastic display effect.

First claim

Opening claim text (preview).

What is claimed is: 1 . A display panel, wherein the display panel comprises a display region and a non-display region, and boundaries between the display region and the non-display region comprise at least one arc structure. 2 . The display panel according to claim 1 , wherein the boundaries comprise two opposite first boundaries and two opposite second boundaries, the first boundaries are constructed in an arc structure, and the second boundaries are constructed in a linear structure. 3 . The display panel according to claim 2 , wherein the display panel comprises an array substrate and a color film substrate, and the shapes of regions in the array substrate and the color filter substrate corresponding to the display region are the same as or corresponding to the shape of the display region. 4 . The display panel according to claim 3 , wherein the array substrate comprises a central region corresponding to the display region and a peripheral wiring region corresponding to the non-display region, the central region comprises gate lines and data lines which are made in crossed arrangement to define pixel regions, and pixels in the pixel regions that are near the arc structure are arranged in accordance with the arc structure. 5 . The display panel according to claim 4 , wherein the gate lines and the data lines define the pixel regions as several lines, and two ends of the several lines of the pixel regions that are respectively near the corresponding are structure of the first boundaries are in an arc shape. 6 . The display panel according to claim 5 , wherein in a direction parallel to the second boundaries, the length of the several lines of the pixel regions are gradually increased from the second boundaries to the top of the are structure of the first boundaries, and in a direction vertical to the second boundaries, the length of the pixel regions are gradually decreased from the top of the arc structure of the first boundaries to two ends of the first boundaries, to form an arc structure corresponding to the arc structure of the first boundaries. 7 . The display panel according to claim 4 , wherein the peripheral wiring region comprises a gate drive chip connected to the gate lines and a source drive chip connected to the data lines, and the wiring structures of the gate lines and the data lines in the peripheral wiring region are arc structures. 8 . The display panel according to claim 5 , wherein the peripheral wiring region comprises a gate drive chip connected to the gate lines and a source drive chip connected to the data lines, and the wiring structures of the gate lines and the data lines in the peripheral wiring region are arc structures. 9 . The display panel according to claim 6 , wherein the peripheral wiring region comprises a gate drive chip connected to the gate lines and a source drive chip connected to the data lines, and the wiring structures of the gate lines and the data lines in the peripheral wiring region are arc structures. 10 . The display panel according to claim 7 , wherein the gate drive chip is provided corresponding to the first boundaries, the gate drive chip provided corresponding to the arc structure comprises arc edges disposed oppositely and linear edges disposed oppositely, and the linear edges are provided parallel to the second boundaries. 11 . The display panel according to claim 10 , wherein the arc edges match the first boundaries of the display region. 12 . The display panel according to claim 10 , wherein the surrounding of the gate drive chip is provided with pins connected with the gate lines, the pins on the arc edges away from the first boundaries extend outwardly along the direction parallel to the second boundaries, and the connection lines of the corresponding pins on the linear edges provided oppositely are constructed in an arc structure corresponding to the shapes of the arc edges. 13 . The display panel according to claim 12 , wherein the pins on the arc edges adjacent to the first boundaries extend along a direction away from the center of the arc edges. 14 . The display panel according to claim 12 , wherein the arc edges adjacent to the first boundaries are divided into a first region and a second region by its central point, the pins in the first region which is located above the central point are inclined upward, and the pins in the second region which is located below the central point are inclined downward. 15 . The display panel according to claim 13 , wherein the arc edges adjacent to the first boundaries are divided into a first region and a second region by its central point, the pins in the first region which is located above the central point are inclined upward, and the pins in the second region which is located below the central point are inclined downward. 16 . A display module, comprising: a display panel and a frame, wherein the display panel is the one according to claim 1 , and the shapes of the inner boundaries of the frame match the shapes of the boundaries of the display region. 17 . The display panel according to claim 16 , wherein the shapes of the outer boundaries of the frame match the shapes of the boundaries of the display region. 18 . The display panel according to claim 16 , wherein the outer boundaries of the frame comprises third boundaries which are provided oppositely and fourth boundaries which are provided oppositely, the third boundaries and the fourth boundaries are both constructed in a linear structure, and a part connecting the third boundaries and the fourth boundaries that are adjacent is constructed in a round corner structure. 19 . The display panel according to claim 18 , wherein the part connecting the third boundaries and the fourth boundaries that are adjacent is provided with a function key. 20 . The display panel according to claim 16 , wherein the outer boundaries of the frame comprise third boundaries which are provided oppositely and constructed in a linear shape and fourth boundaries which are provided oppositely and constructed in an arc structure, and the fourth boundaries are constructed by a linear structure and arc structures connected to two ends of the linear structure.

Assignees

Inventors

Classifications

  • Package configurations · CPC title

  • Interconnections, e.g. scanning lines · CPC title

  • wherein the TFTs are in active matrices · CPC title

  • Conductors connecting driver circuitry and terminals of panels · CPC title

  • Electricity · mapped topic

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What does patent US2016291378A1 cover?
The present invention relates to a display panel and a display module, the display panel comprises a display region and a non-display region, and boundaries between the display region and the non-display region comprise at least one arc structure. The technical effects of the present invention are that it is beneficial to design a display module with an arc and narrow frame, which greatly reduc…
Who is the assignee on this patent?
Boe Tech Co Ltd, Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification G02F1/13452. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Oct 06 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).