Semiconductor device and method for producing semiconductor device

Patent metadata

Field	Value
Publication number	US-2016291248-A1
Application number	US-201615186681-A
Country	US
Kind code	A1
Filing date	Jun 20, 2016
Priority date	Dec 20, 2013
Publication date	Oct 6, 2016
Grant date	—

Abstract

A semiconductor device and a method for producing a semiconductor device are disclosed. The semiconductor device includes: a first silicon layer; a first dielectric layer, located on the first silicon layer, where the first dielectric layer includes a window, and a bottom horizontal size of the window of the first dielectric layer is not greater than 20 nm; and a III-V semiconductor layer, located on the first dielectric layer and in the window of the first dielectric layer, and connected to the first silicon layer in the window of the first dielectric layer. A III-V semiconductor material of the semiconductor device has no threading dislocations, and therefore has relatively high performance.

First claim

What is claimed is:

1 . A method for producing a semiconductor device, comprising:
etching a silicon layer of silicon on insulator (SOI) using a patterned template as a mask, wherein the SOI comprises a silicon substrate, a dielectric layer on the silicon substrate, and the silicon layer on the dielectric layer, and wherein a window of the silicon layer is etched to expose the dielectric layer; etching the dielectric layer using the silicon layer having the window as a template, wherein a window of the dielectric layer is etched to expose the silicon substrate , and wherein the window of the dielectric layer is shaped to limit a size of contact surface exposed over the silicon substrate; and growing a semiconductor material in the window of the dielectric layer to form a buffer layer, wherein the semiconductor material is further grown on the buffer layer to obtain a semiconductor layer, the limited size of the contact surface to reduce threading dislocations of the semiconductor material within the window of the dielectric layer.

2 . The method according to claim 1 , wherein the size of the contact surface is based on a bottom horizontal size of the window of the dielectric layer, and wherein the bottom horizontal size is not greater than 20 nm.

3 . The method according to claim 1 , wherein the semiconductor material is a III-V semiconductor material.

4 . The method according to claim 1 , further comprising:
sheltering a partial region of the patterned template using a photoresist so that the silicon layer under the sheltered region is not etched.

5 . The method according to claim 4 , wherein the method further comprises:
producing a waveguide in the silicon layer that is not etched.

6 . A method for producing a semiconductor device, comprising:
forming a second dielectric layer on a silicon layer of SOI, wherein the SOI comprises a silicon substrate, a first dielectric layer on the silicon substrate, and the silicon layer on the first dielectric layer; etching the second dielectric layer using a patterned template as a mask, and wherein a window of the second dielectric layer is etched to expose the silicon layer, and wherein the window of the second dielectric layer is shaped to limit a size of contact surface exposed over the silicon layer; and growing a semiconductor material in the window of the second dielectric layer to form a buffer layer, wherein the semiconductor material is further grown on the buffer layer to obtain a semiconductor layer, the limited size of the contact surface to reduce threading dislocations of the semiconductor material within the window of the second dielectric layer.

7 . The method according to claim 6 , wherein the size of the contact surface is based on a bottom horizontal size of the window of the second dielectric layer, and wherein the bottom horizontal size is not greater than 20 nm.

8 . The method according to claim 6 , wherein the semiconductor material is a III-V semiconductor material.

9 . The method according to claim 6 , wherein further comprising:
producing a ridge waveguide in the silicon layer.

10 . The method according to claim 9 , wherein further comprising:
sheltering a partial region of the patterned template using a photoresist, wherein a region that is not sheltered by the photoresist corresponds to a position of the ridge waveguide.

11 . A semiconductor device, comprising:
a first silicon layer; a first dielectric layer, which is formed on the first silicon layer, wherein a window of the first dielectric layer is etched to expose the first silicon layer, and wherein the window of the first dielectric layer is shaped to limit a size of contact surface exposed over the first silicon layer; and a semiconductor material layer, wherein the semiconductor material layer is grown on the first dielectric layer, wherein a part of the semiconductor material layer is grown into the window of the first dielectric layer and in contact with the first silicon layer over the contact surface, wherein the limited size of the contact surface is configured to reduce threading dislocations of the semiconductor material layer within the window of the first dielectric layer.

12 . The semiconductor device according to claim 11 , wherein the size of the contact surface is based on a bottom horizontal size of the window of the first dielectric layer, and wherein the bottom horizontal size is not greater than 20 nm.

13 . The semiconductor device according to claim 11 , wherein the semiconductor material is a III-V semiconductor material.

14 . The semiconductor device according to claim 11 , wherein the window of the first dielectric layer is in a shape of an inverted taper or in a shape of a cylinder.

15 . The semiconductor device according to claim 11 , wherein the semiconductor device further comprises:
a second silicon layer on the first dielectric layer, wherein the second silicon layer comprises a waveguide, and wherein the second silicon layer is directly or indirectly connected to the semiconductor material layer to couple light from the semiconductor material layer into the waveguide.

16 . The semiconductor device according to claim 11 , wherein the first silicon layer comprises a waveguide to couple light output from the semiconductor material layer, and wherein the semiconductor device further comprises:
a second dielectric layer under the first silicon layer; and a third silicon layer under the second dielectric layer, wherein the third silicon layer is a silicon substrate.

17 . The semiconductor device according to claim 11 , wherein the semiconductor device is a laser, wherein the semiconductor material layer comprises a buffer layer, an active region, an interlayer, an N-type doped transition layer, and a P-type doped transition layer, and wherein the semiconductor device further comprises an N electrode and a P electrode, wherein the N electrode is connected to the N-type doped transition layer, and the P electrode is connected to the P-type doped transition layer.

18 . The semiconductor device according to claim 11 , wherein the semiconductor device is an optical amplifier, wherein the semiconductor material layer comprises a buffer layer, an active region, an interlayer, an N-type doped transition layer, and a P-type doped transition layer, and wherein
the semiconductor device further comprises an N electrode, a P electrode, and an antireflective film on an end face of the semiconductor material layer, wherein the N electrode is connected to the N-type doped transition layer, the P electrode is connected to the P-type doped transition layer.

19 . The semiconductor device according to claim 11 , wherein the semiconductor device is a photodetector, wherein the semiconductor material layer comprises an N region, a P region, and an intrinsic region, and wherein the semiconductor device further comprises an N electrode and a P electrode, wherein the N electrode is connected to the N region, and the P electrode is connected to the P region.

20 . The semiconductor device according to claim 11 , wherein the semiconductor device is a transistor,
wherein the semiconductor material layer is a channel material of the transistor, and wherein the semiconductor device further comprises a source, a drain, a gate, and a gate dielectric layer, wherein the source, the drain, and the gate dielectric layer are connected to the semiconductor material layer, and the gate is connected to the gate dielectric layer.

Assignees

• Huawei Tech Co Ltd

Inventors

• Huangfu Yourui

Classifications

• H10P14/3242

  Structure · CPC title

• H10P14/3238 Primary

  being insulating materials · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title

• H10P76/204

  of organic photoresist masks · CPC title