Silicon-on-sapphire device with minimal thermal strain preload and enhanced stability at high temperature

Patent metadata

Field	Value
Publication number	US-2016289061-A1
Application number	US-201514679420-A
Country	US
Kind code	A1
Filing date	Apr 6, 2015
Priority date	Apr 6, 2015
Publication date	Oct 6, 2016
Grant date	—

Abstract

A silicon-on-sapphire chip with minimal thermal strain preload is provided. The chip includes a sapphire substrate having a first-sapphire surface and an opposing second-sapphire surface; and a silicon layer overlaying the first-sapphire surface. The silicon layer is formed by: creating a plurality of buried cavities in a plane within tens of microns from a first-silicon surface of a silicon wafer; laser fusing the first-silicon surface to the first-sapphire surface at room temperature to attach the silicon wafer to a sapphire wafer; and cleaving the silicon wafer along the plane including the plurality of buried cavities. A silicon-wafer layer is formed from the silicon material between the first-silicon surface and the plane of the plurality of buried cavities. The silicon-wafer layer and the sapphire wafer form a silicon-on-sapphire wafer. The silicon-on-sapphire chip is formed by dicing the silicon-on-sapphire wafer.

First claim

What is claimed is:

1 . A silicon-on-sapphire chip with minimal thermal strain preload, the chip comprising:
a sapphire substrate having a first-sapphire surface and an opposing second-sapphire surface; and a silicon layer overlaying the first-sapphire surface, the silicon layer formed by:
creating a plurality of buried cavities in a plane within tens of microns from a first-silicon surface of a silicon wafer;
laser fusing at least a portion of the first-silicon surface to at least a portion of the first-sapphire surface at room temperature to attach the silicon wafer to a sapphire wafer, at least a portion of the sapphire wafer including the sapphire substrate;
cleaving the silicon wafer along the plane including the plurality of buried cavities,

wherein a silicon-wafer layer attached to the sapphire wafer is formed from the silicon material between the first-silicon surface and the plane of the plurality of buried cavities, wherein the silicon-wafer layer and the sapphire wafer form a silicon-on-sapphire wafer, and wherein the silicon-on-sapphire chip is formed by dicing the silicon-on-sapphire wafer.

2 . The silicon-on-sapphire chip of claim 1 , wherein the sapphire substrate includes a sapphire cavity opening from the second-sapphire surface, the silicon-on-sapphire chip further comprising:
a pressure sensing diaphragm including;
a sapphire diaphragm formed between a sapphire-cavity floor of the sapphire cavity and the first-sapphire surface; and
a silicon diaphragm including a portion of the silicon layer overlaying the first-sapphire surface and opposing the sapphire-cavity floor of the respective at least one sapphire cavity.

3 . The silicon-on-sapphire chip of claim 1 , further comprising:
at least one non-conductive substrate overlaying at least one of the second-sapphire surface and a second-silicon surface.

4 . The silicon-on-sapphire chip of claim 3 , further including:
at least one via extending through at least one of the at least one non-conductive substrate to electrically contact circuity associated with at least one pressure sensing diaphragm; and substrate circuitry in the at least one of the at least one non-conductive substrate, the substrate circuitry contacting the at least one via extending through the at least one of the at least one non-conductive substrate.

5 . The silicon-on-sapphire chip of claim 1 , wherein the silicon layer overlaying the first-sapphire surface is further processed by polishing the silicon-wafer layer attached to the sapphire wafer after the silicon wafer is cleaved.

6 . The silicon-on-sapphire chip of claim 1 , wherein the plurality of buried cavities are formed by:
implanting hydrogen through the first-silicon surface of the silicon wafer; and heating the silicon wafer.

7 . A silicon-on-sapphire device with minimal thermal strain preload, the device comprising:
a sapphire substrate having a first-sapphire surface and an opposing second-sapphire surface; and a silicon layer having a first-silicon surface and an opposing second-silicon surface, the silicon layer overlaying the first-sapphire surface, the silicon layer formed by:
creating a plurality of buried cavities in a plane within tens of microns from a first-silicon surface of a silicon wafer;
laser fusing, at room temperature, at least a portion of the first-silicon surface to at least a portion of the first-sapphire surface to attach the silicon wafer to the sapphire wafer, at least a portion of the sapphire wafer including the sapphire substrate;
cleaving the silicon wafer along the plane including the plurality of buried cavities,

wherein a silicon-wafer layer attached to the sapphire wafer is formed from the silicon material between the first-silicon surface and the plane of the plurality of buried cavities, wherein the silicon-wafer layer and the sapphire wafer form a silicon-on-sapphire wafer; and
circuitry formed in at least the silicon-wafer layer, wherein the silicon-on-sapphire device is formed by dicing the silicon-on-sapphire wafer.

8 . The silicon-on-sapphire device of claim 7 , wherein the sapphire substrate includes a sapphire cavity opening from the second-sapphire surface, the silicon-on-sapphire device further comprising:
a pressure sensing diaphragm including:
a sapphire diaphragm formed between a sapphire-cavity floor of the sapphire cavity and the first-sapphire surface; and
a silicon diaphragm including a portion of the silicon layer overlaying the first-sapphire surface and opposing the sapphire-cavity floor of the sapphire cavity,

wherein pressure applied to the s pressure sensing diaphragm deflects the pressure sensing diaphragm by an amount proportional to the amount of pressure applied.

9 . The silicon-on-sapphire device of claim 8 , wherein the circuitry formed in at least the silicon layer includes:
at least one bridge-tangential-silicon-piezo resistor formed in the silicon layer tangential to the silicon diaphragm; and at least one bridge-radial-silicon-piezo resistor formed in the silicon layer parallel to a radius of the silicon diaphragm,
wherein the pressure sensing diaphragm, the at least one bridge-tangential-silicon-piezo resistor, and the at least one bridge-radial-silicon-piezo resistor form a piezo-resistive bridge that generates a strain field proportional to the amount of pressure applied.

10 . The silicon-on-sapphire device of claim 8 , further comprising:
a sealed mounting package configured to withstand high-pressure and high-temperature, and configured to enclose all but the pressure sensing diaphragm of the silicon-on-sapphire device.

11 . The silicon-on-sapphire chip of claim 8 , further comprising:
a non-conductive substrate overlaying a second-sapphire surface, the second-sapphire surface opposing the first sapphire surface.

12 . The silicon-on-sapphire chip of claim 11 , further including:
at least one via extending from the non-conductive substrate to electrically contact circuity associated with at least one of the pressure sensing diaphragm; and substrate circuitry in the non-conductive substrate contacting the at least one via.

13 . The silicon-on-sapphire device of claim 8 , further comprising:
a sealed mounting package configured to withstand high-pressure and high-temperature, wherein the circuitry is configured to sense a pressure applied to the pressure sensing diaphragm.

14 . The silicon-on-sapphire device of claim 7 , further comprising:
a sapphire cover forming at least one pressure sensing diaphragm overlaying the second-silicon surface of the silicon layer, the sapphire cover encasing at least one reference vacuum in contact with the second-silicon surface.

15 . A method of forming a silicon-on-sapphire chip with minimal thermal strain preload, the method comprising:
creating a plurality of buried cavities in a plane within tens of microns from a first-silicon surface of a silicon wafer; laser fusing, at room temperature, at least a portion of the first-silicon surface to at least a portion of a first-sapphire surface of a sapphire wafer to attach the silicon wafer to the sapphire wafer; cleaving the silicon wafer along the plane including the plurality of buried cavities wherein a silicon-wafer layer attached to the sapphire wafer is formed from the silicon material between the first-silicon surface and the plane of the plurality of buried cavities; polishing the silicon-wafer layer attached to the sapphire wafer, wherein the silicon-wafer layer and the sapphire wafer form a silicon-on-sapphire wafer; and dicing the silicon-on-sapphi

Assignees

• Honeywell Int Inc

Inventors

• Brown Gregory C

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1916

  with separation or delamination along an ion implanted layer, e.g. Smart-cut · CPC title

• H10D86/03

  wherein the substrate comprises sapphire, e.g. silicon-on-sapphire [SOS] · CPC title

• B81C2203/037

  Thermal bonding techniques not provided for in B81C2203/035 - B81C2203/036 · CPC title

• B81B2207/094

  Feed-through, via · CPC title