Metal substrate with insulated vias

Patent metadata

Field	Value
Publication number	US-2016286644-A1
Application number	US-201615154198-A
Country	US
Kind code	A1
Filing date	May 13, 2016
Priority date	Oct 24, 2013
Publication date	Sep 29, 2016
Grant date	—

Abstract

A metal substrate with insulated vias (MSIV) has a metallic layer with through-holes defined through a thickness of the layer, a dielectric layer formed on part of the surface of the metallic layer and extending to cover internal walls of the through-hole, a conductive material extending through the insulated through-hole to form an insulated via, and an electrical circuit formed on a portion of the dielectric layer in thermal and/or electrical contact with the conductive via. The dielectric layer is a dielectric nanoceramic layer having an equiaxed crystalline structure with an average grain size of 500 nanometres or less, a thickness of between 0.1 and 100 micrometres, a dielectric strength of greater than 20 KV mm −1 , and a thermal conductivity of greater than 3 W/mK. Such a MSIV can be used as an electronic substrate to support devices such as power, microwave, optoelectronic, solid-state lighting and thermoelectric devices.

First claim

1 : A metal substrate with insulated vias (MSIV), comprising:
a metallic layer having a through-hole defined through a thickness of the metallic layer between a first surface and a second surface of the metallic layer; a dielectric layer formed at least in part by oxidation of the metallic layer, the dielectric layer being formed as a continuous layer on at least one of the first surface and the second surface of the metallic layer, and on internal walls of the through-hole; a conductive metallic via extending through the through-hole defined in the metallic layer, the conductive metallic via being electrically insulated from the metallic layer by the dielectric layer; and an electrical circuit formed on a portion of the dielectric layer, the electrical circuit being in electrical contact or thermal contact or both electrical and thermal contact with the conductive metallic via, wherein the dielectric layer is a dielectric nanoceramic layer having an equiaxed crystalline structure with an average grain size of 500 nanometres or less, a thickness of between 0.1 and 100 micrometres, a dielectric strength of greater than 20 KV mm −1 , and a thermal conductivity of greater than 3 W/mK, and wherein at least a portion of the dielectric nanoceramic layer is impregnated with organic or non-organic material.

2 : A MSIV according to claim 1 , wherein the dielectric nanoceramic layer includes grains having an average grain size of 100 nanometres or less.

3 : A MSIV according to claim 1 , wherein the dielectric nanoceramic layer has a thickness of between 1 micrometre and 50 micrometres.

4 : A MSIV according to claim 1 , wherein the metallic layer has a thickness of between 5 micrometres and 5000 micrometres.

5 : A MSIV according to claim 1 ,
wherein the dielectric nanoceramic layer is formed as a continuous layer on both the first surface and the second surface of the metallic layer and on the internal walls of the through-hole, and wherein first and second electrical circuits are formed on portions of the dielectric nanoceramic layer formed on both the first and second surfaces of the metallic layer, respectively, the first and second electrical circuits being electrically connected or thermally connected or both electrically and thermally connected by the conductive metallic via.

6 : A MSIV according to claim 1 , wherein in which the metallic layer has a plurality of through-holes defined through the thickness thereof, with internal walls of each of the plurality of through-holes being coated with a portion of the dielectric nanoceramic layer.

7 : A MSIV according to claim 1 , wherein the through-hole has a diameter of between 20 micrometres and 2000 micrometres.

8 : A MSIV according to claim 1 , wherein the metallic layer has a plurality of through-holes of between 50 and 200 micrometres in diameter formed through the thickness of the metallic layer, with a spacing between the through-holes being between 50 and 200 micrometres.

9 : A MSIV according to claim 1 , further comprising at least one more metallic layer, each metallic layer having at least one through-hole with internal walls coated with a dielectric nanoceramic material having properties of the dielectric nanoceramic layer.

10 : A MSIV according to claim 1 , wherein the MSIV is a flexible electronic substrate (FES) having a minimum bend radius of lower than 25 cm.

11 : A MSIV according to claim 1 , wherein the metallic layer is formed of a metal selected from a group of metals that includes aluminium, magnesium, titanium, zirconium, tantalum, beryllium, or from an alloy of the group, or from an intermetallic of any of the metals of the group.

12 : A MSIV according to claim 1 , wherein the MSIV is formed entirely of non-organic materials.

13 : A MSIV according to claim 1 , wherein the MSIV has a maximum operating temperature in excess of 200° C.

14 : A MSIV according to claim 1 , wherein the dielectric nanoceramic layer has a dielectric constant of greater than 7.

15 : A MSIV according to claim 1 , wherein the dielectric nanoceramic layer is formed by electrochemical oxidation of the metallic layer in an alkaline colloidal electrolyte.

16 : A MSIV according to claim 1 , wherein in which the electrical circuit is formed by one of: a screen printing process, a conductive ink jet printing process, a electroless metallisation process, a galvanic metallisation process, a process that includes adhesive bonding of metal foil, a process that includes bonding of pre-fabricated flex circuits, a metal sputtering process, a chemical vapour deposition (CVD) process, and a physical vapour deposition (PVD) metallisation process.

17 : A MSIV according to claim 1 , wherein the organic or non-organic material includes a polyimide material, a methacrylate material, an epoxy resin material, an acrylic resin material or a sol-gel material.

18 : A method of forming a metal substrate with insulated vias (MSIV) the method, comprising the steps of:
providing a metallic layer; defining through-holes through a thickness of the metallic layer between a first surface and a second surface of the metallic layer; forming a dielectric nanoceramic layer on at least one of the first surface and the second surface of the metallic layer and on internal walls of the through-hole, the dielectric layer being formed at least in part by oxidation of the metallic layer; impregnating at least a portion of the dielectric nanoceramic layer with organic or non-organic material; filling the through-hole with conductive material to form a conductive via; and forming an electrical circuit on a portion of the dielectric nanoceramic layer, the electrical circuit being in electrical contact or thermal contact or both electrical and thermal contact with the conductive via, wherein the dielectric nanoceramic layer has an equiaxed crystalline structure with an average grain size of 500 nanometres or less, a thickness of between 0.1 and 100 micrometres, a dielectric strength of greater than 20 KV mm −1 , and a thermal conductivity of greater than 3 W/mK.

19 : A method according to claim 18 , wherein the dielectric nanoceramic layer is formed by electrochemical oxidation of the metallic layer in an alkaline colloidal electrolyte.

20 : A method according to claim 18 , wherein the electrical circuit is formed by one of: a screen printing process, a conductive ink jet printing process, a electroless metallisation process, a galvanic metallisation process, a process that includes adhesive bonding of metal foil, a process that includes bonding of pre-fabricated flex circuits, a metal sputtering process, a chemical vapour deposition (CVD) process, and a physical vapour deposition (PVD) metallisation process.

21 : A method according to claim 18 , wherein the organic or non-organic material includes a polyimide material, a methacrylate material, an epoxy resin material, an acrylic resin material, or a sol-gel material.

22 : A MSIV according to claim 1 , wherein the MSIV is incorporated as part of a multilayered substrate.

23 . A MSIV according to claim 1 , wherein the MSIV supports any one or a combination of: an electronic chip or die, an electronic device, a display, a battery, an optoelectronic device, an RF device, a microwave device, a thermoelectric device, and an electrical device.

24 : A method according to claim 18 , wherein, in the impregnating step, the dielectric nanoceramic layer is impregnated wi

Assignees

• Cambridge Nanotherm Ltd
• Rogers Corp

Inventors

• Shashkov Pavel
• Usov Sergey
• Curtis Steven
• Kilhenny Brett W

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/536

  the connected ends being ball-shaped · CPC title

• H10W70/02

  of conductive package substrates serving as an interconnection, e.g. of metal plates (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/635

  Through-vias · CPC title