Storage system, information processor, and computer-readable recording medium having stored therein program for generating parity

US2016285474A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016285474-A1
Application numberUS-201615055677-A
CountryUS
Kind codeA1
Filing dateFeb 29, 2016
Priority dateMar 27, 2015
Publication dateSep 29, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

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A storage system includes a first information processor, a second information processor, and a superorainate device. The first information processor includes a first memory device that stores therein the data, a difference generator that generates difference data representing a difference between updating data received from the superordinate device and the data stored in the first memory device before updating, a second memory device stores therein the generated difference data, and a data transmitter that transmits the stored difference data to the second information processor. The second information processor includes a third memory device that stores therein the parity, a data receiver that receives the difference data transmitted from the data transmitter, and a parity difference applier that generates a post-updating parity that is to be written into the third memory device by applying the received difference data to the stored parity before the updating.

First claim

Opening claim text (preview).

What is claimed is: 1 . A storage system comprising: a first information processor that stores therein data; a second information processor that is communicably connected to the first information processor and that stores therein a parity of the data; and a superordinate device that is communicably connected to the first information processor, the first information processor comprising: a first memory device that stores therein the data; a difference generator that generates difference data representing a difference between updating data received. from the superordinate device and the data stored in the first memory device before updating; a second memory device stores therein the difference data generated by the difference generator; and a data transmitter that transmits the difference data stored in the second memory device to the second information processor, the second information processor comprising: a third memory device that stores therein the parity; a data receiver that receives the difference data transmitted. from the data transmitter; and a parity difference applier that generates a post-updating parity that is to be written into the third memory device by applying the difference data received by the data receiver to the parity stored in the third memory device before the updating. 2 . The storage system according to claim 1 , the first information processor further comprising a data difference applier that generates post-updating data that is to be written into the first memory device by applying the difference data stored in the second memory device to the data stored in the first memory device before the updating. 3 . The storage system according to claim 1 , wherein the difference generator generates the difference data by calculation using the updating data received from the superordinate device and the data stored in the first memory device before the updating on a Galois Field. 4 . The storage system according to claim 1 , wherein the difference data to be stored in the second memory device is used as a journal of data to be written into the first memory device and a parity to be written into the third memory device. 5 . An information processor that is communicably connected to a superordinate device and a second information processor that stores a parity of data, the information processor comprising: a first memory device that stores therein the data; a difference generator that generates difference data representing a difference between updating data received from the superordinate device and the data stored in the first memory device before updating; a second memory device stores therein the difference data generated by the difference generator; and a data transmitter that transmits the difference data stored in the second memory device to the second information processor, the difference data being used for generating a post-updating parity in the second information processor. 6 . The information processor according to claim 5 , further comprising a data difference applier that generates post-updating data that is to be written into the first memory device by applying the difference data stored in the second memory device to the data stored in the first memory device before the updating. 7 . The information processor according to claim 5 , wherein the difference generator generates the difference data by calculation using the updating data received from the superordinate device and the data stored in the first memory device before the updating on a Galois Field. 8 . The information processor according to claim 5 , wherein the difference data to be stored in the second memory device is used as a journal of data to be written into the first memory device and a parity to be stored in the second information processor. 9 . A non-transitory computer-readable recording medium having stored therein a program for generating a parity, the program causing a computer provided for an information processor that is communicably connected to a superordinate device and a second information processor that stores a parity of data to execute: generating difference data representing a difference between updating data received from the superordinate device and the data stored in a first memory device provided for the information processor before updating; storing the generated difference data in a second memory device provided for the first information processor; and transmitting the difference data stored in the second memory device to the second information processor, the difference data being used for generating a post-updating parity in the second information processor. 10 . The non-transitory computer-readable recording medium according to claim 9 , wherein the program further causes the computer to execute generating post-updating data that is to be written into the first memory device by applying the difference data stored in the second memory device to the data stored in the first memory device before the updating. 11 . The non-transitory computer-readable recording medium according to claim 9 , wherein the program further causes the computer to execute generating the difference data by calculation using the updating data received from the superordinate device and the data stored in the first memory device before the updating on a Galois Field. 12 . The non-transitory computer-readable recording medium according to claim 9 , wherein the difference data to be stored in the second memory device is used as a journal of data to be written into the first memory device and a parity to be stored in the second information processor.

Assignees

Inventors

Classifications

  • Specific encoding aspects, e.g. encoding by means of decoding · CPC title

  • using code combining, i.e. using combining of codeword portions which may have been transmitted separately, e.g. Digital Fountain codes, Raptor codes or Luby Transform [LT] codes · CPC title

  • Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title

  • Parity data distribution in semiconductor storages, e.g. in SSD · CPC title

  • Parity-single bit-RAID5, i.e. RAID 5 implementations · CPC title

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What does patent US2016285474A1 cover?
A storage system includes a first information processor, a second information processor, and a superorainate device. The first information processor includes a first memory device that stores therein the data, a difference generator that generates difference data representing a difference between updating data received from the superordinate device and the data stored in the first memory device…
Who is the assignee on this patent?
Fujitsu Ltd
What technology area does this patent fall under?
Primary CPC classification H03M13/3761. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Sep 29 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).