Fault tolerant design for large area nitride semiconductor devices

Patent metadata

Field	Value
Publication number	US-2016284829-A1
Application number	US-201415032824-A
Country	US
Kind code	A1
Filing date	Oct 28, 2014
Priority date	Aug 4, 2009
Publication date	Sep 29, 2016
Grant date	—

Abstract

A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighbouring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid devices.

First claim

1 . A device structure for a nitride semiconductor transistor comprising:
a substrate having a nitride semiconductor layer formed on a device area of the substrate, the nitride semiconductor layer defining a plurality of active regions for an array of islands of a multi-island transistor, the array of islands extending in first and second directions over the device area, each of said active regions comprising a two dimensional electron gas (2DEG) region isolated from adjacent active regions by an intervening inactive region of the device area; each island having a source electrode, a drain electrode and a gate electrode formed on a respective active region of the island, each source electrode having a plurality of source peninsulas, each drain electrode having a plurality of drain peninsulas, the source and drain peninsulas being interleaved and spaced apart over the active region of the island to define a channel region therebetween, the gate electrode being formed on the nitride semiconductor layer over the channel region and running between the source and drain peninsulas across the island; each source electrode having a source contact area, each drain electrode having a drain contact area and each gate electrode having a gate contact area; and the source, drain and gate electrodes of each island of the array of islands being arranged so that each island is electrically isolated from the source, drain and gate electrodes of neighbouring islands in at least one of said first and second directions.

2 . The device structure of claim 1 wherein the source, drain and gate electrode contact areas of individual islands each comprise a contact pad having at least a minimum size of 25 μm required for electrical probing and testing for identification of defective islands.

3 . The device structure of claim 2 wherein: the array of islands comprises an n×m matrix of n rows and m columns of islands.

4 . The device structure of claim 3 wherein, for i=1 to n, the source contact areas and gate contact areas of the ith and i−1th rows of islands are arranged in rows, positioned over inactive regions of the device area between the i−1th and ith rows of islands; and drain contact areas of the ith and i+1th rows of islands are arranged in rows, positioned over inactive regions of the device area between the ith and i+1th rows of islands.

5 . The device structure of claim 3 wherein the transistor further comprises an overlying interconnect structure comprising at least one dielectric layer and at least one metallization layer providing:
a source interconnection interconnecting in parallel the source electrodes of sets of multiple islands;
a drain interconnection interconnecting in parallel the drain electrodes of sets of multiple islands; and
a gate interconnection interconnecting the gate electrodes of multiple islands to form a common gate.

6 . The device structure of claim 5 wherein said source, drain and gate interconnections are provided selectively to respective source, drain and gate electrodes of islands, excluding defective islands, to provide electrical isolation of defective islands.

7 . The device structure of claim 2 , comprising defective islands, and further comprising a layer of electrically insulating material that is patterned to isolate at least one of the gate contact, source contact and drain contact of each defective island thereby providing electrical isolation of the defective islands before fabrication of an overlying interconnect structure for respective gate, source and drain interconnections.

8 . The device structure of claim 1 wherein the source and drain electrodes of each island of the array are arranged such that:
in the first direction, except at edges of the array, each source electrode is positioned adjacent to a source electrode of a neighbouring island, and each drain electrode is adjacent to a drain electrode of a neighbouring island, so as to provide isolation comprising an inactive region between neighbouring islands in the first direction;
in the second direction, except at edges of the array, at least some source electrodes are positioned adjacent a source electrode of a neighbouring island, and at least some drain electrodes are positioned adjacent a drain electrode, so as to provide isolation comprising an inactive region between sets of neighbouring islands in the second direction; and
each source electrode, each drain electrode and each gate electrode having a respective contact pad, each contact pad being located over the inactive region of the substrate extending between islands in the first direction.

9 . The device structure of claim 8 wherein, in the second direction, except at edges of the array, each source electrode is positioned adjacent a source electrode of a neighbouring island, and each drain electrode is positioned adjacent a drain electrode so as to provide isolation comprising an inactive region between each neighbouring island in the second direction.

10 . The device structure of claim 8 wherein, in the second direction, except at edges of the array, for a set of islands, a side of at least one source electrode is positioned adjacent a source electrode of a neighbouring island, and/or a side of at least one drain electrode is positioned adjacent a drain electrode so as to provide isolation comprising an inactive region between sets of neighbouring islands in the second direction.

11 . The device structure of claim 8 wherein the array comprises an array of rows and columns of islands, and for each group of four islands, the source and drain electrodes are arranged to provide isolation between each row of islands.

12 . The device structure of claim 8 wherein, the array comprises an array of rows and columns of islands, arranged as a repeating pattern of a group of four islands, wherein the source and drain electrodes are arranged to provide isolation between at least each row of islands.

13 . The device structure of claim 12 wherein source electrodes of neighbouring cells in the first and second directions are coupled to form a common source electrode for each neighbouring pair of rows of islands.

14 . The device structure of claim 13 wherein the source and drain electrodes are further arranged to provide an active region between each column of islands.

15 . The device of claim 14 wherein source electrodes of adjacent islands in a row direction are interconnected to form a common source across at least part of the row.

16 . The device structure of claim 13 wherein said contact areas to the respective source electrodes and drain electrodes are provided on promontories of each respective source and drain electrode, said promontories extending over the inactive region.

17 . The device structure of claim 8 wherein said contact areas to the respective source electrodes and drain electrodes are provided on promontories of each respective source and drain electrode, said promontories being tapered and extending over the inactive region between rows of islands.

18 . The device structure of claim 13 wherein, for a normally-on device, for each island, the contact area of the gate electrode is arranged over the inactive region in the vicinity of the source contact of the respective island.

19 . The device structure according to claim 8 comprising a centre-fed gate arrangement wherein respective gate contacts of each island pair in a first direction are centered over the inactive region between each island pair and a gate connection connecting a centre region of each island

Assignees

• Gan Systems Inc

Inventors

• Klowak Greg P
• Mcknight-Macneil Cameron
• Tweddle Howard
• Mizan Ahmad
• Springett Nigel

Classifications

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10P74/232

  comprising connection or disconnection of parts of a device in response to a measurement · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10W20/484

  Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes · CPC title

• H10W20/43

  Layouts of interconnections · CPC title