Chip package assembly and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2016284663-A1
Application number	US-201615050587-A
Country	US
Kind code	A1
Filing date	Feb 23, 2016
Priority date	Mar 23, 2015
Publication date	Sep 29, 2016
Grant date	—

Abstract

In one embodiment, a chip package assembly can include: a first substrate at a bottom layer, the first substrate having a first surface and a second surface opposite to the first surface, where the second surface is provided with a first group of inner leads; at least one chip layer above the first group of inner leads, where each of the chip layers comprises a third surface and a fourth surface opposite to the third surface, where electrodes on the third surface that that lie at the lowest level are electrically coupled to the first group of inner leads through a first connector; and a second substrate above the fourth surface on the topmost layer and having a fifth surface, and where the fifth surface is provided with a second group of inner leads electrically coupled to the electrodes on the fourth surface on the topmost layer.

First claim

What is claimed is:

1 . A chip package assembly, comprising:
a) a first substrate at a bottom layer, the first substrate having a first surface and a second surface opposite to said first surface, wherein said second surface is provided with a first group of inner leads; b) at least one chip layer above said first group of inner leads, wherein each of said chip layers comprises a third surface and a fourth surface opposite to said third surface, wherein electrodes on said third surface that that lie at the lowest level are electrically coupled to said first group of inner leads through a first connector; c) a second substrate above said fourth surface on the topmost layer and having a fifth surface, wherein said fifth surface is provided with a second group of inner leads electrically coupled to the electrodes on said fourth surface on the topmost layer, and wherein said second substrate comprises a sixth surface opposite to said fifth surface; d) a plastic package in the space between said first and second substrates, wherein side surfaces of said plastic package expose said first and second groups of inner leads; and e) first and second groups of outer leads on the side surfaces of said plastic package, being configured to electrically couple with said first and second groups of inner leads, and extending to said second surface or said sixth surface.

2 . The chip package assembly of claim 1 , wherein said plastic package comprises:
a) a first side surface that exposes said first group of inner leads; and b) a second side surface opposite to said first side surface, and that exposes said second group of inner leads, wherein said first group of outer leads are arranged on said first side surface and extending to said second surface or to one side of said sixth surface, and wherein said second group of outer leads are arranged on the other side of said second surface and extending to said second surface or to the other side of said sixth surface.

3 . The chip package assembly of claim 2 , wherein said first connector comprises silver epoxy soldering tin, or a first eutectic layer above said first group of inner leads and a second eutectic layer above said third surface, wherein said first and second eutectic layers form a eutectic connection.

4 . The chip package assembly of claim 3 , wherein said second connector comprises a eutectic connection having third eutectic layer on electrodes of said fourth surface and a fourth eutectic layer on said second group of inner leads, conductive bumps, or soldering bumps between electrodes of said fourth surface and said second group of inner leads.

5 . The chip package assembly of claim 4 , wherein said third eutectic layer comprises a titanium-nickel-silver alloy layer, and wherein said fourth eutectic layer comprises a silver metal layer or a tin metal layer.

6 . The chip package assembly of claim 4 , wherein first ends of said first and second groups of outer leads extend to two sides of said second surface, and second ends of said first and second groups of outer leads extend to two sides of said sixth surface.

7 . The chip package assembly of claim 6 , wherein each of said first group of outer leads and said second group of outer leads comprises a copper layer or a silver layer that connected with said plastic package, and a thin layer above said copper layer or said silver layer.

8 . The chip package assembly of claim 2 , wherein said package assembly comprises:
a) a plurality of chip layers, an interlayer inner lead group between every two of said chip layers, and an interlayer outer lead group on the side surface of said plastic package and that extends to said second surface or said sixth surface; b) wherein electrodes on each of said third surfaces that are above said third surface at the lowermost level are electrically coupled to the interlayer inner lead group below through a first middle connector; c) wherein the electrodes on each of said fourth surfaces that are above said fourth surface at the topmost layer are electrically coupled to the interlayer inner lead group above through a second middle connector; and d) said interlayer inner lead group being exposed on the side surface of said plastic package and electrically coupled with said interlayer outer lead group.

9 . The chip package assembly of claim 8 , wherein said plastic package comprises a plurality of plastic package layers, and each of said plastic package layers covers one chip layer.

10 . A method of making a chip package assembly, the method comprising:
a) forming a patterned conductive layer on a first surface of a first substrate as a first group of inner leads, wherein said first substrate comprises a second surface opposite said first surface; b) placing at least one chip on a first group of inner leads, wherein each of said chips comprises a third surface and a fourth surface opposite to said third surface, wherein the electrodes on said third surface at the lowermost level are electrically coupled to said first group of inner leads through a first connector; c) electrically coupling said second group of inner leads on a fifth surface of a second substrate to said electrodes on said fourth surface of the topmost layer through a second connector; d) filling a molding compound between said first and second substrates to form a plastic package, and exposing said first and second groups of inner leads on said side surface of said plastic package; and e) forming first and second groups of outer leads on the side surface of said plastic package for electrical coupling with said first and second groups of inner leads, wherein said first and second groups of outer leads extend to said second surface or a sixth surface of said second substrate, wherein said sixth surface is opposite to said fifth surface.

11 . The method of claim 10 , wherein said plastic package comprises:
a) a first side surface exposing said first group of inner leads, a second side surface opposite to said first side surface and exposing said second group of inner leads; and b) said first group of outer leads being arranged on said first side surface and extending to said second surface or one side of said sixth surface, wherein said second group of outer leads are arranged on the other side of said second surface and extend to said second surface or the other side of said sixth surface.

12 . The method of claim 11 , further comprising forming a patterned conductive layer on said fifth surface as said second group of inner leads before electrically connecting said second group of inner leads to the electrodes on said fourth surface through said second connector.

13 . The method of claim 12 , further comprising forming said first connector of silver epoxy or soldering tin, or forming said first connector by a first eutectic layer above said first group of inner leads, and a second eutectic layer above said third surface, wherein said first and second eutectic layers form a eutectic connection.

14 . The method of claim 13 , wherein said second connector comprises a eutectic connection having a third eutectic layer on electrodes of said fourth surface and a fourth eutectic layer on the second group of inner leads, conductive bumps, or soldering bumps between electrodes of said fourth surface and said second group of inner leads.

15 . The method of claim 14 , further comprising forming a titanium nickel silver alloy layer on the electrodes of said fourth surface as said third eutectic layer, and forming a silver metal layer or a tin metal layer on said second group of inner leads.

Assignees

• Silergy Semiconductor Technology Hangzhou Ltd

Inventors

• Ye Jiaming
• Shentu Junli

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/07336

  Soldering or alloying · CPC title