Dynamic integrated circuit fabrication methods

Patent metadata

Field	Value
Publication number	US-2016284609-A1
Application number	US-201514671265-A
Country	US
Kind code	A1
Filing date	Mar 27, 2015
Priority date	Mar 27, 2015
Publication date	Sep 29, 2016
Grant date	—

Abstract

Methods and processes for forming semiconductor devices with reduced yield loss and failed dies are provided. One method includes, for instance: obtaining a wafer after at least one fabrication processing; taking first r, θ, z measurements of the wafer after the at least one fabrication processing; performing at least one second fabrication processing; taking second r, θ, z measurements of the wafer after the at least one second fabrication processing; and analyzing the second r, θ, z measurements with respect to the first r, θ, z measurements. A process includes, for instance: obtaining a wafer with a substrate and at least one first device positioned on the substrate; taking first measurements in a r, θ, z coordinate system; forming at least one second device over the substrate; taking second measurements in the r, θ, z coordinate system; and analyzing the second measurements with respect to the first measurements.

First claim

What is claimed is:

1 . A method comprising:
obtaining a wafer after at least one fabrication processing; taking first r, θ, z measurements of the wafer after the at least one fabrication processing; performing at least one second fabrication processing; taking second r, θ, z measurements of the wafer after the at least one second fabrication processing; and analyzing the second r, θ, z measurements with respect to the first r, θ, z measurements.

2 . The method of claim 1 , further comprising:
performing a first regression modeling with the first r, θ, z measurements to determine first critical dimension measurements; performing a second regression modeling with the first r, θ, z measurements to determine first overlay measurements; and performing a third regression modeling with the first r, θ, z measurements to determine first thickness measurements.

3 . The method of claim 2 , further comprising:
performing a first regression modeling with the second r, θ, z measurements to determine second critical dimension measurements; performing a second regression modeling with the second r, θ, z measurements to determine second overlay measurements; and performing a third regression modeling with the second r, θ, z measurements to determine second thickness measurements.

4 . The method of claim 3 , further comprising:
comparing the second critical dimension measurements to the first critical dimension measurements; comparing the second overlay measurements to the first overlay measurements; and comparing the second thickness measurements to the first thickness measurements.

5 . The method of claim 4 , further comprising:
performing at least one third fabrication processing; taking third r, θ, z measurements of the wafer after the at least one third fabrication processing; and analyzing the third r, θ, z measurements with respect to the first r, θ, z measurements and the second r, θ, z measurements.

6 . The method of claim 5 , further comprising:
performing a first regression modeling with the third r, θ, z measurements to determine third critical dimension measurements; performing a second regression modeling with the third r, θ, z measurements to determine third overlay measurements; and performing a third regression modeling with the third r, θ, z measurements to determine third thickness measurements.

7 . The method of claim 6 , wherein analyzing the third r, θ, z measurements with respect to the first r, θ, z measurements and the second r, θ, z measurements comprises:
comparing the third critical dimension measurements to the first and second critical dimension measurements;
comparing the third overlay measurements to the first and second overlay measurements; and
comparing the third thickness measurements to the first and second thickness measurements.

8 . The method of claim 4 , further comprising:
calculating available area in the wafer for at least one third fabrication processing; and determining if the at least one third fabrication processing has a critical dimension and overlay to be positioned in the open area.

9 . The method of claim 8 , further comprising:
adjusting critical dimensions and overlay of the at least one third fabrication processing.

10 . The method of claim 4 , further comprising:
analyzing the first and second critical dimension measurements, first and second overlay measurements, and first and second thickness measurements to determine a number of chips on the wafer with critical dimension and overlay errors.

11 . A process comprising:
obtaining a wafer with a substrate and at least one first device positioned on the substrate; taking first measurements in a r, θ, z coordinate system; forming at least one second device over the substrate; taking second measurements in the r, θ, z coordinate system; and analyzing the second measurements with respect to the first measurements.

12 . The process of claim 11 , further comprising:
determining first critical dimension measurements by performing a first regression analysis with the first measurements; determining first overlay measurements by performing a second regression analysis with the first measurements; and determining first thickness measurements by performing a third regression analysis with the first measurements.

13 . The process of claim 12 , further comprising:
determining second critical dimension measurements by performing a fourth regression analysis with the second measurements; determining second overlay measurements by performing a fifth regression analysis with the second measurements; and determining second thickness measurements by performing a sixth regression analysis with the second measurements.

14 . The process of claim 13 , further comprising:
evaluating the fourth regression analysis and the first regression analysis; evaluating the fifth regression analysis and the second regression analysis; and evaluating the sixth regression analysis and the third regression analysis.

15 . The process of claim 14 , further comprising:
forming at least one third device over the substrate; taking third measurements in the r, θ, z coordinate system; and comparing the third measurements to the first measurements and second measurements.

16 . The process of claim 15 , further comprising:
determining third critical dimension measurements by performing a seventh regression analysis with the third measurements; determining third overlay measurements by performing an eighth regression analysis with the third measurements; and determining third thickness measurements by performing a ninth regression analysis with the third measurements.

17 . The process of claim 16 , wherein comparing the third measurements to the first measurements and second measurements comprises:
comparing the seventh regression analysis to the first regression analysis and the fourth regression analysis; comparing the eighth regression analysis to the second regression analysis and the fifth regression analysis; and comparing the ninth regression analysis to the third regression analysis and the sixth regression analysis.

18 . The device of claim 14 , further comprising:
calculating an open area between the at least one first device and the at least one second device; and determining if critical dimensions and overlay of at least one third device position the at least one third device in the open area.

19 . The device of claim 18 , further comprising:
adjusting the critical dimensions and overlay of the at least one third device before fabricating the at least one third device to position the at least one third device in the open area.

20 . The device of claim 14 , further comprising:
analyzing the first, second, third, fourth, fifth, and sixth regression analyses to determine a number of chips on the wafer with critical dimension and overlay errors.

Assignees

• Globalfoundries Inc

Inventors

• Park Dongsuk
• CHO Wangkeun
• Cheng Wen Hua

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/23 Primary

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H01L22/20 Primary

  Electricity · mapped topic

• G01B21/04

  by measuring coordinates of points · CPC title

• G01B21/08

  for measuring thickness · CPC title