Encapsulated dies with enhanced thermal performance

Patent metadata

Field	Value
Publication number	US-2016284570-A1
Application number	US-201615173037-A
Country	US
Kind code	A1
Filing date	Jun 3, 2016
Priority date	Mar 25, 2015
Publication date	Sep 29, 2016
Grant date	—

Abstract

The present disclosure relates to a semiconductor package having encapsulated dies with enhanced thermal performance. The semiconductor package includes a carrier, an etched flip chip die attached to a top surface of the carrier, a first mold compound, and a second mold compound. The etched flip chip die includes a device layer and essentially does not include a substrate. The first mold compound resides on the top surface of the carrier, surrounds the etched flip chip die, and extends beyond a top surface of the etched flip chip die to form a cavity, to which the top surface of the etched flip chip die is exposed. The second mold compound fills the cavity and is in contact with the top surface of the etched flip chip die. The second mold compound having a high thermal conductivity improves thermal performance of the etched flip chip die.

First claim

What is claimed is:

1 . An apparatus comprising:
a carrier having a top surface; an etched flip chip die comprising a device layer attached to the top surface of the carrier, wherein at least a portion of a substrate of the etched flip chip die has been removed from the etched flip-chip die; a first mold compound residing on the top surface of the carrier, surrounding the etched flip chip die, and extending beyond a top surface of the etched flip chip die to form a cavity within the first mold compound, wherein the top surface of the etched flip chip die is exposed at a bottom of the cavity; and a second mold compound filling the cavity and in contact with the top surface of the etched flip chip die.

2 . The apparatus of claim 1 wherein the substrate of the etched flip chip die has been removed completely from the etched flip-chip die, such that the top surface of the etched flip chip die exposed at the bottom of the cavity is a top surface of the device layer.

3 . The apparatus of claim 1 wherein at least 95% of the substrate of the etched flip chip die has been removed from the etched flip-chip die.

4 . The apparatus of claim 1 wherein the second mold compound further resides over the first mold compound.

5 . The apparatus of claim 1 wherein a top surface of the second mold compound is planarized.

6 . The apparatus of claim 1 wherein the second mold compound has high thermal conductivity between 2.5 w/m·k and 10 w/m·k.

7 . The apparatus of claim 1 wherein the second mold compound has a thermal conductivity greater than 2.5 w/m·k.

8 . The apparatus of claim 1 wherein the second mold compound has a thermal conductivity greater than 10 w/m·k.

9 . The apparatus of claim 1 wherein the carrier is one of a group consisting of a laminate, a wafer level fan out (WLFO) carrier, a lead frame, and a ceramic carrier.

10 . The apparatus of claim 1 wherein the first mold compound is an organic epoxy resin system.

11 . The apparatus of claim 1 wherein the device layer includes at least one of a group consisting of diodes, transistors, mechanical switches, and resonators.

12 . The apparatus of claim 1 wherein a thickness of the device layer is 4-7 μm.

13 . The apparatus of claim 1 wherein the first mold compound and the second mold compound are formed from different materials.

14 . The apparatus of claim 13 wherein the second mold compound has a thermal conductivity between 2.5 w/m·k and 10 w/m·k.

15 . The apparatus of claim 13 wherein the second mold compound has a thermal conductivity greater than 2.5 w/m·k.

16 . The apparatus of claim 13 wherein the second mold compound has a thermal conductivity greater than 10 w/m·k.

Assignees

• Rf Micro Devices Inc

Inventors

• Morris Thomas Scott
• Jandzinski David
• Parker Stephen
• Chadwick Jon
• Costa Julio C

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title