System, method and apparatus for energy efficiency and energy conservation by configuring power management parameters during run time

Patent metadata

Field	Value
Publication number	US-2016282919-A1
Application number	US-201615174779-A
Country	US
Kind code	A1
Filing date	Jun 6, 2016
Priority date	Apr 19, 2012
Publication date	Sep 29, 2016
Grant date	—

Abstract

According to one embodiment of the invention, a processor includes a power control unit, an interface to software during runtime that permits the software to set a plurality of power management constraint parameters for the power control unit during runtime of the processor without a reboot of the processor, and a storage element to store a respective lock bit for each of the plurality of power management constraint parameters to disable the interface from changing a respective constraint parameter when set.

First claim

1 . A method comprising:
providing an interface of a processor to software during runtime that permits the software to set a plurality of power management constraint parameters for a power control unit of the processor during runtime of the processor without a reboot of the processor; and clearing a respective lock bit for each of the plurality of power management constraint parameters on a reset event of the processor, wherein each lock bit disables the interface from changing a respective constraint parameter when set.

2 . The method of claim 1 , further comprising setting a global lock bit to cause the setting of the respective lock bit for each of the plurality of power management constraint parameters.

3 . The method of claim 1 , wherein the plurality of power management constraint parameters comprises a first set of constraints for when the processor is running a first application and a second set of constraints for when the processor is running a second application.

4 . The method of claim 1 , wherein the plurality of power management constraint parameters comprises a first consumption target for when the processor is running a first application and a second consumption target for when the processor is running a second application.

5 . The method of claim 1 , wherein the plurality of power management constraint parameters comprises a first set of constraints for when the processor is running a first combination of applications and a second set of constraints for when the processor is running a second combination of applications.

6 . The method of claim 1 , wherein the plurality of power management constraint parameters comprises a first consumption target for when the processor is running a first combination of applications and a second consumption target for when the processor is running a second combination of applications.

7 . The method of claim 1 , wherein the clearing comprises only clearing the respective lock bit for each of the plurality of power management constraint parameters on a reset event of the processor.

8 . The method of claim 1 , wherein the plurality of power management constraint parameters are overclocking constraint parameters.

9 . A processor comprising:
a power control unit; an interface to software during runtime that permits the software to set a plurality of power management constraint parameters for the power control unit during runtime of the processor without a reboot of the processor; and a storage element to store a respective lock bit for each of the plurality of power management constraint parameters to disable the interface from changing a respective constraint parameter when set.

10 . The processor of claim 9 , wherein the storage element comprises a global lock bit field that when set is to cause the respective lock bit for each of the plurality of power management constraint parameters to be set .

11 . The processor of claim 9 , wherein the plurality of power management constraint parameters comprises a first set of constraints for when the processor is to run a first application and a second set of constraints for when the processor is to run a second application.

12 . The processor of claim 9 , wherein the plurality of power management constraint parameters comprises a first consumption target for when the processor is to run a first application and a second consumption target for when the processor is to run a second application.

13 . The processor of claim 9 , wherein the plurality of power management constraint parameters comprises a first set of constraints for when the processor is to run a first combination of applications and a second set of constraints for when the processor is to run a second combination of applications.

14 . The processor of claim 9 , wherein the plurality of power management constraint parameters comprises a first consumption target for when the processor is to run a first combination of applications and a second consumption target for when the processor is to run a second combination of applications.

15 . The processor of claim 9 , wherein the processor is to only clear the respective lock bit for each of the plurality of power management constraint parameters on a reset event of the processor.

16 . The processor of claim 9 , wherein the plurality of power management constraint parameters are overclocking constraint parameters.

17 . A non-transitory computer-readable storage medium storing code that when executed by a computer causes the computer to perform a method comprising:
providing an interface of a processor to software during runtime that permits the software to set a plurality of power management constraint parameters for a power control unit of the processor during runtime of the processor without a reboot of the processor; and clearing a respective lock bit for each of the plurality of power management constraint parameters on a reset event of the processor, wherein each lock bit disables the interface from changing a respective constraint parameter when set.

18 . The non-transitory computer-readable storage medium of claim 17 , wherein the method further comprises setting a global lock bit to cause the setting of the respective lock bit for each of the plurality of power management constraint parameters.

19 . The non-transitory computer-readable storage medium of claim 17 , wherein the plurality of power management constraint parameters comprises a first set of constraints for when the processor is running a first application and a second set of constraints for when the processor is running a second application.

20 . The non-transitory computer-readable storage medium of claim 17 , wherein the plurality of power management constraint parameters comprises a first consumption target for when the processor is running a first application and a second consumption target for when the processor is running a second application.

21 . The non-transitory computer-readable storage medium of claim 17 , wherein the plurality of power management constraint parameters comprises a first set of constraints for when the processor is running a first combination of applications and a second set of constraints for when the processor is running a second combination of applications.

22 . The non-transitory computer-readable storage medium of claim 17 , wherein the plurality of power management constraint parameters comprises a first consumption target for when the processor is running a first combination of applications and a second consumption target for when the processor is running a second combination of applications.

23 . The non-transitory computer-readable storage medium of claim 17 , wherein the clearing comprises only clearing the respective lock bit for each of the plurality of power management constraint parameters on a reset event of the processor.

24 . The non-transitory computer-readable storage medium of claim 17 , wherein the plurality of power management constraint parameters are overclocking constraint parameters.

Assignees

• Intel Corp

Inventors

• Wells Ryan D
• Jahagirdar Sanjeev S
• Sodhi Inder M
• Shrall Jeremy J
• Gunther Stephen H
• Ragland Daniel J
• Adams Nicholas J

Classifications

• G06F1/3203 Primary

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G06F1/28 Primary

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

• G06F9/4421

  Physics · mapped topic

• G06F9/44505

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• G06F9/4401

  Bootstrapping (security arrangements therefor G06F21/57) · CPC title