System, method and apparatus for energy efficiency and energy conservation by configuring power management parameters during run time

Patent metadata

Field	Value
Publication number	US-9360909-B2
Application number	US-201313843405-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Apr 19, 2012
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

According to one embodiment of the invention, an integrated circuit device at least one compute engine and a control unit. Coupled to the compute engine(s), the control unit is adapted to dynamically control an energy-efficient operating setting of at least one power management parameter for the integrated circuit device after execution of Basic Input/Output System (BIOS) has already completed.

First claim

What is claimed is:

1. A method comprising:
providing an interface of a processor to application software during runtime that permits at least one of a user and said application software to set a power management constraint for a power control unit of the processor during runtime of said processor without a reboot of the processor, wherein the power management constraint comprises a plurality of constraint parameters and the method further comprises clearing a respective lock bit for each of the plurality of constraint parameters on a reset event of the processor, wherein each lock bit disables the interface from changing a respective constraint parameter when set.

2. The method of claim 1 , wherein the interface of the processor permits the user and the application software to set the power management constraint during runtime of the processor without the reboot of the processor.

3. The method of claim 1 , wherein the power management constraint comprises a first set of constraints for when the processor is running a first application and a second set of constraints for when the processor is running a second application specified by the user.

4. The method of claim 1 , wherein the power management constraint comprises a first consumption target for when the processor is running a first application and a second consumption target for when the processor is running a second application specified by the user.

5. The method of claim 1 , wherein the power management constraint comprises a first set of constraints for when the processor is running a first combination of applications and a second set of constraints for when the processor is running a second combination of applications specified by the user.

6. The method of claim 1 , wherein the power management constraint comprises a first consumption target for when the processor is running a first combination of applications and a second consumption target for when the processor is running a second combination of applications specified by the user.

7. The method of claim 1 , further comprising clearing a lock bit on a reset event of the processor, wherein the lock bit disables the interface when set.

8. The method of claim 1 , wherein the plurality of constraint parameters are overclocking constraint parameters.

9. A processor comprising:
a power control unit; and
an interface to application software during runtime that permits at least one of a user and said application software to set a power management constraint for the power control unit during runtime of said processor without a reboot of the processor, wherein the power management constraint comprises a plurality of constraint parameters and the processor further comprises at least one register to store a respective lock bit for each of the plurality of constraint parameters to disable the interface from changing a respective constraint parameter when set.

10. The processor of claim 9 , wherein the interface of the processor is to permit the user and the application software to set the power management constraint during runtime of the processor without the reboot of the processor.

11. The processor of claim 9 , wherein the power management constraint comprises a first set of constraints for when the processor is to run a first application and a second set of constraints for when the processor is to run a second application to be specified by the user.

12. The processor of claim 9 , wherein the power management constraint comprises a first consumption target for when the processor is to run a first application and a second consumption target for when the processor is to run a second application to be specified by the user.

13. The processor of claim 9 , wherein the power management constraint comprises a first set of constraints for when the processor is to run a first combination of applications and a second set of constraints for when the processor is to run a second combination of applications to be specified by the user.

14. The processor of claim 9 , wherein the power management constraint comprises a first consumption target for when the processor is to run a first combination of applications and a second consumption target for when the processor is to run a second combination of applications to be specified by the user.

15. The processor of claim 9 , further comprising a register to store a lock bit to disable the interface when set.

16. The processor of claim 9 , wherein the plurality of constraint parameters are overclocking constraint parameters.

17. A non-transitory computer-readable storage medium storing code that when executed by a computer causes the computer to perform a method comprising:
providing an interface of a processor to application software during runtime that permits at least one of a user and said application software to set a power management constraint for a power control unit of the processor during runtime of said processor without a reboot of the processor, wherein the power management constraint comprises a plurality of constraint parameters and the method further comprises clearing a respective lock bit for each of the plurality of constraint parameters on a reset event of the processor, wherein each lock bit disables the interface from changing a respective constraint parameter when set.

18. The non-transitory computer-readable storage medium of claim 17 , wherein the interface of the processor permits the user and the application software to set the power management constraint during runtime of the processor without the reboot of the processor.

19. The non-transitory computer-readable storage medium of claim 17 , wherein the power management constraint comprises a first set of constraints for when the processor is running a first application and a second set of constraints for when the processor is running a second application specified by the user.

20. The non-transitory computer-readable storage medium of claim 17 , wherein the power management constraint comprises a first consumption target for when the processor is running a first application and a second consumption target for when the processor is running a second application specified by the user.

21. The non-transitory computer-readable storage medium of claim 17 , wherein the power management constraint comprises a first set of constraints for when the processor is running a first combination of applications and a second set of constraints for when the processor is running a second combination of applications specified by the user.

22. The non-transitory computer-readable storage medium of claim 17 , wherein the power management constraint comprises a first consumption target for when the processor is running a first combination of applications and a second consumption target for when the processor is running a second combination of applications specified by the user.

23. The non-transitory computer-readable storage medium of claim 17 , the method further comprising clearing a lock bit on a reset event of the processor, wherein the lock bit disables the interface when set.

24. The non-transitory computer-readable storage medium of claim 1 , wherein the plurality of constraint parameters are overclocking constraint parameters.

Assignees

• Wells Ryan D
• Jahagirdar Sanjeev
• Sodhi Inder
• Shrall Jeremy
• Gunther Stephen
• Ragland Daniel
• Adams Nicholas
• Intel Corp

Inventors

• Wells Ryan D
• Jahagirdar Sanjeev
• Sodhi Inder
• Shrall Jeremy
• Gunther Stephen
• Ragland Daniel
• Adams Nicholas

Classifications

• G06F1/3203 Primary

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• Y02B60/1217

  Cross-Sectional Technologies · mapped topic

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• Y02B60/1285

  Cross-Sectional Technologies · mapped topic