Array substrate, manufacturing method for the same, display device and electronic product

Patent metadata

Field	Value
Publication number	US-2016276378-A1
Application number	US-201414414713-A
Country	US
Kind code	A1
Filing date	Apr 8, 2014
Priority date	Dec 31, 2013
Publication date	Sep 22, 2016
Grant date	—

Abstract

According to the method for manufacturing an array substrate of the present disclosure, when two non-adjacent conductive layers are electrically connected to each other through the via-holes, the insulating layers between the adjacent conductive layers may be etched by several etching processes so as to form the corresponding via-holes in the insulating layer, thereby to achieve the electrical connection between the non-adjacent conductive layers. Meanwhile, it is also able to achieve the electrical connection between the adjacent conductive layers through the via-holes in each etching process. In other words, when at least three conductive layers are electrically connected with each other through the via-holes, merely the insulating layer between the adjacent conductive layers is etched in each etching process.

First claim

What is claimed is:

1 . An array substrate, comprising:
a first metal layer, a first insulating layer, a second metal layer, a second insulating layer and a first conductive layer sequentially formed on a base substrate, wherein the first metal layer includes a first connection pattern, the first insulating layer includes a first via-hole, the second metal layer includes a second connection pattern, the second insulating layer includes a transition via-hole and a second via-hole, the first via-hole corresponds to a position where the first connection pattern is located, the transition via-hole corresponds to a position where the first via-hole is located, the first metal layer is electrically connected to the first conductive layer through the first via-hole and the transition via-hole, the second via-hole corresponds to a position where the second connection pattern is located, and the second metal layer is electrically connected to the first conductive layer through the second via-hole.

2 . The array substrate according to claim 1 , further comprising a second conductive layer on the first insulating layer, wherein the second conductive layer is formed at the first via-hole corresponding to the first connection pattern.

3 . The array substrate according to claim 1 , wherein a first electrical connection pattern is arranged between the first via-hole and the transition via-hole, and the first electrical connection pattern and the second metal layer are made of an identical material.

4 . The array substrate according to claim 3 , wherein the first metal layer is electrically connected to the first conductive layer through the first via-hole, the first electrical connection pattern and the transition via-hole.

5 . The array substrate according to claim 2 , wherein a pixel electrode is formed on the first insulating layer, and the pixel electrode is formed by the second conductive layer.

6 . The array substrate according to claim 5 , wherein the second conductive layer is a second transparent conductive layer with high transmittance, and a pattern of the first insulating layer and a pattern of the second transparent conductive layer are formed simultaneously by a single patterning process.

7 . The array substrate according to claim 1 , wherein the first conductive layer is made of Indium Tin Oxide (ITO) and/or Indium Zinc Oxide (IZO).

8 . A display device at least comprising an array substrate,
wherein the array substrate comprises: a first metal layer, a first insulating layer, a second metal layer, a second insulating layer and a first conductive layer sequentially formed on a base substrate, wherein the first metal layer includes a first connection pattern, the first insulating layer includes a first via-hole, the second metal layer includes a second connection pattern, the second insulating layer includes a transition via-hole and a second via-hole, the first via-hole corresponds to a position where the first connection pattern is located, the transition via-hole corresponds to a position where the first via-hole is located, the first metal layer is electrically connected to the first conductive layer through the first via-hole and the transition via-hole, the second via-hole corresponds to a position where the second connection pattern is located, and the second metal layer is electrically connected to the first conductive layer through the second via-hole.

9 . The display device according to claim 8 , wherein the array substrate further comprises a second conductive layer on the first insulating layer, and the second conductive layer is formed at the first via-hole corresponding to the first connection pattern.

10 . The display device according to claim 8 , wherein a first electrical connection pattern is arranged between the first via-hole and the transition via-hole, and the first electrical connection pattern and the second metal layer are made of an identical material.

11 . The display device according to claim 10 , wherein the first metal layer is electrically connected to the first conductive layer through the first via-hole, the first electrical connection pattern and the transition via-hole.

12 . The display device according to claim 9 , wherein a pixel electrode is formed on the first insulating layer, and the pixel electrode is formed by the second conductive layer.

13 . The display device according to claim 12 , wherein the second conductive layer is a second transparent conductive layer with high transmittance, and a pattern of the first insulating layer and a pattern of the second transparent conductive layer are formed simultaneously by a single patterning process.

14 . The display device according to claim 8 , wherein the first conductive layer is made of Indium Tin Oxide (ITO) and/or Indium Zinc Oxide (IZO).

15 . A method for manufacturing an array substrate, comprising the steps of:
forming a first metal layer on a base substrate, and performing a patterning process on the first metal layer so as to form a pattern including a first connection pattern; forming a first insulating layer on the first metal layer, and performing a patterning process on the first insulating layer so as to form one or more first via-holes corresponding to a position where the first connection pattern is located; forming a second metal layer on the first insulating layer, and performing a patterning process on the second metal layer so as to form a pattern including a second connection pattern; forming a second insulating layer on the second metal layer, and performing a patterning process on the second insulating layer so as to form one or more transition via-holes corresponding to positions where the first via-holes are located and one or more second via-holes corresponding to a position where the second connection pattern is located; and forming a pattern including a first conductive layer on the second insulating layer.

16 . The method according to claim 15 , wherein the step of forming the first insulating layer on the first metal layer and performing a patterning process on the first insulating layer so as to form one or more first via-holes comprises:
applying a first photoresist onto the first insulating layer, and exposing and developing the first photoresist by using a half-tone or gray-tone mask, so as to form a first photoresist unreserved region corresponding to at least a region where the first via-holes are located; and removing the first insulating layer corresponding to the first photoresist unreserved region by an etching process, so as to form the first via-holes.

17 . The method according to claim 15 , wherein the step of forming the first insulating layer on the first metal layer and performing the patterning process on the first insulating layer so as to form one or more first via-holes further comprises forming a pattern including a second conductive layer on the first insulating layer.

18 . The method according to claim 17 , wherein the step of forming a pattern including the second conductive layer on the first insulating layer comprises:
exposing and developing the first photoresist by using the half-tone or gray-tone mask so as to form a first photoresist partially-reserved region corresponding to at least a region where a pattern of the second conductive layer is located; and removing the photoresist at the first photoresist partially-reserved region by an ashing process, forming a second transparent conductive thin film on the photoresist and removing the remaining photoresist, so as to form the

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co

Inventors

• Bai Jinchao
• Liu Yao
• Li Liangliang
• Ding Xiangqian
• Guo Zongie

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• G02F1/133345

  Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence) · CPC title