Wafer transport method

Patent metadata

Field	Value
Publication number	US-2016276186-A1
Application number	US-201514658867-A
Country	US
Kind code	A1
Filing date	Mar 16, 2015
Priority date	Mar 16, 2015
Publication date	Sep 22, 2016
Grant date	—

Abstract

A wafer transport method is provided. The wafer transport method includes loading an initial carrier containing a first wafer and a second wafer on a first semiconductor apparatus, and processing the first wafer by the first semiconductor apparatus, and loading the first wafer into a first carrier disposed on the first semiconductor apparatus. The wafer transport method also includes processing the second wafer by the first semiconductor apparatus, and loading the second wafer into a second carrier disposed on the first semiconductor apparatus. The wafer transport method further includes processing the first wafer by a second semiconductor apparatus, and loading the first wafer into an integration carrier disposed on the second semiconductor apparatus. The wafer transport method further includes processing the second wafer by the second semiconductor apparatus, and loading the second wafer into the integration carrier disposed on the second semiconductor apparatus.

First claim

What is claimed is:

1 . A wafer transport method, comprising:
loading an initial carrier containing a first wafer and a second wafer on a first semiconductor apparatus; processing the first wafer by the first semiconductor apparatus, and loading the first wafer into a first carrier disposed on the first semiconductor apparatus; processing the second wafer by the first semiconductor apparatus, and loading the second wafer into a second carrier disposed on the first semiconductor apparatus; processing the first wafer by a second semiconductor apparatus, and loading the first wafer into an integration carrier disposed on the second semiconductor apparatus; and processing the second wafer by the second semiconductor apparatus, and loading the second wafer into the integration carrier disposed on the second semiconductor apparatus.

2 . The wafer transport method as claimed in claim 1 , further comprising assigning a first group code to the first wafer and a second group code to the second wafer when the first wafer and the second wafer are contained in the initial carrier.

3 . The wafer transport method as claimed in claim 2 , further comprising deleting the first group code and the second group code after the first wafer and the second wafer are loaded in the integration wafer.

4 . The wafer transport method as claimed in claim 1 , wherein the first wafer and the second wafer processed by the first semiconductor apparatus have a quality-control time in a range from about 30 minutes to about 120 minutes.

5 . The wafer transport method as claimed in claim 1 , further comprising loading the first carrier on the first semiconductor apparatus before the first wafer is processed by the first semiconductor apparatus, wherein the first carrier is an empty carrier.

6 . The wafer transport method as claimed in claim 1 , further comprising loading the second carrier on the first semiconductor apparatus before the second wafer is processed by the first semiconductor apparatus, wherein the second carrier is an empty carrier.

7 . The wafer transport method as claimed in claim 1 , further comprising loading the integration carrier on the second semiconductor apparatus before the first wafer is processed by the second semiconductor apparatus, wherein the integration carrier is an empty carrier.

8 . A wafer transport method, comprising:
loading an initial carrier containing a plurality of wafers on a first semiconductor apparatus; assigning a first group code to some of the wafers and a second group code to some of the wafers; processing the wafers by the first semiconductor apparatus; loading the wafers relative to the first group code into a first carrier disposed on the first semiconductor apparatus, and loading the wafers relative to the second group code into a second carrier disposed on the first semiconductor apparatus; processing the wafers in the first carrier by a second semiconductor apparatus, and processing the wafers in the second carrier by the second semiconductor apparatus; and loading the wafers relative to the first group code and the second group code into an integration carrier disposed on the second semiconductor apparatus.

9 . The wafer transport method as claimed in claim 8 , further comprising processing a diving process according the number of the wafers and a quality-control time of the wafers.

10 . The wafer transport method as claimed in claim 8 , wherein the wafers processed by the first semiconductor apparatus have a quality-control time in a range from about 30 minutes to about 120 minutes.

11 . The wafer transport method as claimed in claim 8 , further comprising loading the first carrier and the second carrier on the first semiconductor apparatus in sequence, wherein the first carrier and the second carrier are empty carriers.

12 . The wafer transport method as claimed in claim 8 , further comprising loading the integration carrier on the second semiconductor apparatus before the wafers relative to the first group code are processed by the second semiconductor apparatus, wherein the integration carrier is an empty carrier.

13 . The wafer transport method as claimed in claim 8 , further comprising deleting the first group code and the second group code after the wafers are loaded in the integration wafer.

14 . A wafer transport method, comprising:
loading an initial carrier containing a plurality of first wafers and a plurality of second wafers on a first semiconductor apparatus; processing the first wafers by the first semiconductor apparatus, and loading the first wafers into a first carrier disposed on the first semiconductor apparatus; processing the second wafers by the first semiconductor apparatus, and loading the second wafers into a second carrier disposed on the first semiconductor apparatus; processing the first wafers by a second semiconductor apparatus; processing the second wafers by a third semiconductor apparatus; processing the first wafers by a fourth semiconductor apparatus, and loading the first wafers into an integration carrier disposed on the fourth semiconductor apparatus; and processing the second wafers by the fourth semiconductor apparatus, and loading the second wafers into the integration carrier disposed on the fourth semiconductor apparatus.

15 . The wafer transport method as claimed in claim 14 , further comprising assigning a first group code to the first wafers and a second group code to the second wafers when the first wafer and the second wafer are contained in the initial carrier.

16 . The wafer transport method as claimed in claim 15 , further comprising deleting the first group code and the second group code after the first wafers and the second wafers are loaded in the integration wafer.

17 . The wafer transport method as claimed in claim 14 , wherein the first wafers and the second wafers processed by the first semiconductor apparatus have a quality-control time in a range from about 30 minutes to about 120 minutes, the first wafers processed by the second semiconductor apparatus have a quality-control time in a range from about 30 minutes to about 120 minutes, and the second wafers processed by the third semiconductor apparatus have a quality-control time in a range from about 30 minutes to about 120 minutes.

18 . The wafer transport method as claimed in claim 14 , further comprising loading the first carrier and the second carrier on the first semiconductor apparatus in sequence, wherein the first carrier and the second carrier are empty carriers.

19 . The wafer transport method as claimed in claim 14 , further comprising loading the first wafers into the first carrier after the first wafers are processed by the second semiconductor apparatus, and loading the second wafers into the second carrier after the second wafers are processed by the third semiconductor apparatus.

20 . The wafer transport method as claimed in claim 14 , further comprising loading the integration carrier on the second semiconductor apparatus, wherein the integration carrier is an empty carrier.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Jyun-Chao
• Chen Ming-Jung
• Ku Shao-Yen
• Su Tsai-Pao

Classifications

• H10P72/10

  using carriers specially adapted therefor, e.g. front opening unified pods [FOUP] · CPC title

• H10P72/3304

  characterised by movements or sequence of movements of transfer devices · CPC title

• H10P72/0612

  Production flow monitoring, e.g. for increasing throughput · CPC title

• H10P72/0618 Primary

  using identification means, e.g. labels on substrates or labels on containers · CPC title

• H01L21/677

  Electricity · mapped topic