Gate off delay compensation circuit and light apparatus having the same

Patent metadata

Field	Value
Publication number	US-2016270171-A1
Application number	US-201615051371-A
Country	US
Kind code	A1
Filing date	Feb 23, 2016
Priority date	Mar 13, 2015
Publication date	Sep 15, 2016
Grant date	—

Abstract

A gate off delay compensation circuit includes a sensing interval determiner configured to determine an interval in which a driving voltage corresponds to a first and second level of a reference voltage as a driving voltage sensing interval, a driving voltage excess interval determiner configured to determine a driving voltage excess interval defined as an interval in which the driving voltage is larger than the reference voltage and a driving voltage period determiner configured to determine a period of the driving voltage based on the driving voltage sensing interval and the driving voltage excess interval. Therefore, a gate off delay compensation circuit 100 decreases an average driving current and an average driving voltage and allows decrease of a variation of a driving current according to a change of a input voltage V IN .

First claim

What is claimed is:

1 . A gate off delay compensation circuit, comprising:
a sensing interval determiner configured to determine an interval in which a driving voltage corresponds to a first level and second level of a reference voltage as a driving voltage sensing interval; a driving voltage excess interval determiner configured to determine a driving voltage excess interval defined as an interval in which the driving voltage is larger than the reference voltage; and a driving voltage period determiner configured to determine a period of the driving voltage based on the driving voltage sensing interval and the driving voltage excess interval.

2 . The gate off delay compensation circuit of claim 1 , wherein the sensing interval determiner comprises a reference voltage generator configured to receive a dimming voltage related to a light brightness to generate the reference voltage.

3 . The gate off delay compensation circuit of claim 2 , wherein the reference voltage generator comprises a Digital Analog Converter (DAC) configured to output a voltage corresponding to a value of current induced by the dimming voltage.

4 . The gate off delay compensation circuit of claim 3 , wherein the reference voltage generator further comprises a voltage follower configured to follow the output voltage to generate the reference voltage.

5 . The gate off delay compensation circuit of claim 1 , wherein the sensing interval determiner comprises a voltage divider configured to divide the reference voltage into a first interval reference voltage having a first level and a second interval reference voltage having a second level.

6 . The gate off delay compensation circuit of claim 1 , wherein the sensing interval determiner comprises a period determination voltage generator configured to generate each of a first period determination voltage and a second period determination voltage by charging and discharging each of a first capacitor and a second capacitor, wherein the first capacitor and the second capacitor have different capacitances.

7 . The gate off delay compensation circuit of claim 1 , wherein the sensing interval determiner comprises:
a first capacitor configured to respond to the reference voltage, to be charged from an initial point of the period to an end point of the period, and to be discharged in the driving voltage excess interval; and a second capacitor configured to be charged during the driving voltage sensing interval.

8 . The gate off delay compensation circuit of claim 7 , wherein the sensing interval determiner comprises:
a first switching element connected to a terminal of the first capacitor in series and a second switching element connected to the terminal in parallel, wherein the first switching element receives a first enable signal at the initial point of the period and the second switching element receives a second enable signal at an initial point of the driving voltage excess interval.

9 . The gate off delay compensation circuit of claim 7 , wherein the sensing interval determiner comprises:
a third switching element connected to a terminal of the second capacitor in series and a fourth switching element connected to the terminal in parallel, wherein the third switching element receives a third enable signal at an initial point of the driving voltage sensing interval and the fourth switching element receives a fourth enable signal at an end point of the driving voltage sensing interval.

10 . The gate off delay compensation circuit of claim 1 , wherein the driving voltage excess interval determiner receives a first interval reference voltage and a second interval reference voltage, the reference voltage and the driving voltage to generate a first enable signal, a second enable signal, a third enable signal or a fourth enable signal.

11 . The gate off delay compensation circuit of claim 1 , wherein the driving voltage excess interval determiner provides a first enable signal, a second enable signal, a third enable signal or a fourth enable signal to respectively control a first switching element, a second switching element, a third switching element or a fourth switching element.

12 . The gate off delay compensation circuit of claim 1 , wherein the driving voltage period determiner receives a first period determination voltage and a second period determination voltage from the sensing interval determiner to generate a driving signal.

13 . The gate off delay compensation circuit of claim 1 , wherein the driving voltage period determiner provides a driving signal from an initial point of the period to a initial point of the driving voltage excess interval.

14 . A light emitting diode light apparatus, comprising:
Light Emitting Diodes (LEDs); a bridge diode configured to full-wave rectify an alternating current (AC) input voltage; and a gate off delay compensation circuit configured to receive a driving power supply to drive the LEDs, wherein the gate off delay compensation circuit comprises a sensing interval determiner configured to determine an interval in which a driving voltage corresponds to a first level and second level of a reference voltage as a driving voltage sensing interval, a driving voltage excess interval determiner configured to determine a driving voltage excess interval defined as an interval in which the driving voltage is larger than the reference voltage and a driving voltage period determiner configured to determine a period of the driving voltage based on the driving voltage sensing interval and the driving voltage excess interval.

15 . A circuit, comprising:
a driving voltage period determiner configured to determine a period of a driving voltage based on a driving voltage sensing interval and a driving voltage excess interval, wherein the driving voltage sensing interval is an interval in which a driving voltage corresponds to a first level and second level of a reference voltage and the driving voltage excess interval is defined as an interval in which the driving voltage is larger than the reference voltage.

16 . The circuit of claim 15 , further comprising a sensing interval determiner configured to determine the driving voltage sensing interval.

17 . The circuit of claim 16 , wherein the sensing interval determiner comprises a voltage divider configured to divide the reference voltage into a first interval reference voltage having a first level and a second interval reference voltage having a second level.

18 . The circuit of claim 16 , wherein the sensing interval determiner comprises a period determination voltage generator configured to generate each of a first period determination voltage and a second period determination voltage by charging and discharging each of a first capacitor and a second capacitor, wherein the first capacitor and the second capacitor have different capacitances.

19 . The circuit of claim 16 , wherein the sensing interval determiner comprises:
a first capacitor configured to respond to the reference voltage, to be charged from an initial point of the period to an end point of the period, and to be discharged in the driving voltage excess interval; and a second capacitor configured to be charged during the driving voltage sensing interval.

20 . The circuit of claim 15 , further comprising a driving voltage excess interval determiner configured to determine the driving voltage excess interval.

Assignees

• Magnachip Semiconductor Ltd

Inventors

• Lim Gyu Ho
• Yoon Jong Hyun
• Cui zhi yuan
• RYU Yong Gi

Classifications

• H05B33/0845

  Electricity · mapped topic

• H05B33/0815 Primary

  Electricity · mapped topic

• Y02B20/30

  Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED] · CPC title

• H05B45/395

  Linear regulators · CPC title

• H05B45/10 Primary

  Controlling the intensity of the light · CPC title