Methods to form high density through-mold interconnections

Patent metadata

Field	Value
Publication number	US-2016268231-A1
Application number	US-201414767471-A
Country	US
Kind code	A1
Filing date	Sep 15, 2014
Priority date	Sep 15, 2014
Publication date	Sep 15, 2016
Grant date	—

Abstract

Methods of fabricating a microelectronic device comprising forming a microelectronic substrate having a plurality microelectronic device attachment bond pads and at least one interconnection bond pad formed in and/or on an active surface thereof, attaching a microelectronic device to the plurality of microelectronic device attachment bond pads, forming a mold chase having a mold body and at least one projection extending from the mold body, wherein the at least one projection includes at least one sidewall and a contact surface, contacting the mold chase projection contact surface to a respective microelectronic substrate interconnection bond pad, disposing a mold material between the microelectronic substrate and the mold chase, and removing the mold chase to form at least one interconnection via extending from a top surface of the mold material to a respective microelectronic substrate interconnection bond pad.

First claim

1 - 25 . (canceled)

26 . A method of fabricating a microelectronic device comprising:
forming a microelectronic substrate having a plurality of microelectronic device attachment bond pads and at least one interconnection bond pad formed in and/or on an active surface thereof; attaching a microelectronic device to the plurality of microelectronic device attachment bond pads; forming a mold chase having a mold body and at least one projection extending from the mold body, wherein the at least one projection includes at least one sidewall and a contact surface; contacting the at least one mold chase projection contact surface to a respective microelectronic substrate interconnection bond pad; disposing a mold material between the microelectronic substrate and the mold chase; and removing the mold chase to form at least one interconnection via extending from a top surface of the mold material to a respective microelectronic substrate interconnection bond pad.

27 . The method of claim 26 , further comprising filling the at least one interconnection via with a conductive material to form a through-mold interconnection.

28 . The method of claim 26 , further comprising curing the mold material prior the removing the mold chase.

29 . The method of claim 26 , wherein disposing the mold material comprises disposing the mold material between the microelectronic substrate and the mold chase to substantially encapsulate the microelectronic device and surrounds the at least one interconnection projection sidewall.

30 . The method of claim 26 , wherein forming the mold chase comprises forming a portion of the at least one mold chase projection proximate and including the mold chase projection contact surface from a resilient material.

31 . The method of claim 26 , wherein forming the microelectronic substrate comprises forming a microelectronic substrate having an active surface with a plurality microelectronic device attachment bond pads and at least one interconnection bond pad having a protective bump formed in and/or on the microelectronic substrate active surface.

32 . The method of claim 31 , wherein forming the microelectronic substrate comprises forming the protective bump from a solder material.

33 . The method of claim 26 , wherein contacting the mold chase projection contact surface to a respective microelectronic substrate interconnection bond pad comprises contacting the mold chase projection contact surface to a respective protective bump of the microelectronic substrate interconnection bond pad.

34 . The method of claim 26 , wherein the at least one mold chase projection has a cross section shape having a width greater than a height.

35 . A method of fabricating a package-on-package microelectronic device comprising:
forming a first package comprising:
forming a microelectronic substrate having a plurality microelectronic device attachment bond pads and at least one interconnection bond pad formed in and/or on an active surface thereof;
attaching a microelectronic device to the plurality of microelectronic device attachment bond pads;
forming a mold chase having a mold body and at least one projection extending from the mold body, wherein the at least one projection includes at least one sidewall and a contact surface;
contacting the at least one mold chase projection contact surface to a respective microelectronic substrate interconnection bond pad;
disposing a mold material between the microelectronic substrate and the mold chase; and
removing the mold chase to form at least one interconnection via extending from a top surface of the mold material to a respective microelectronic substrate interconnection bond pad; and
filling the at least one interconnection via with a conductive material to form at least one through-mold interconnection;
and
attaching a second package to the first package, wherein an electrically connection is formed from the second package to the at least one through-mold interconnect of the first package.

36 . The method of claim 35 , further comprising curing the mold material prior the removing the mold chase.

37 . The method of claim 35 , wherein disposing the mold material comprises disposing the mold material between the microelectronic substrate and the mold chase to substantially encapsulate the microelectronic device and surrounds the at least one interconnection projection sidewall.

38 . The method of claim 35 , wherein forming the mold chase comprises forming a portion of the at least one mold chase projection proximate and including the mold chase projection contact surface from a resilient material.

39 . The method of claim 35 , wherein forming the microelectronic substrate comprises forming a microelectronic substrate having an active surface with a plurality microelectronic device attachment bond pads and at least one interconnection bond pad having a protective bump formed in and/or on the microelectronic substrate active surface.

40 . The method of claim 39 , wherein forming the microelectronic substrate comprises forming the protective bump from a solder material.

41 . The method of claim 35 , wherein contacting the mold chase projection contact surface to a respective microelectronic substrate interconnection bond pad comprises contacting the mold chase projection contact surface to a respective protective bump of the microelectronic substrate interconnection bond pad.

42 . The method of claim 35 , wherein the at least one mold chase projection has a cross section shape having a width greater than a height.

43 . A method of fabricating an electronic system, comprising:
forming a board; and attaching a package-on-package microelectronic device on the board, wherein the package-on-package microelectronic device formed by:
forming a first package comprising:
forming a microelectronic substrate having a plurality microelectronic device attachment bond pads and at least one interconnection bond pad formed in and/or on an active surface thereof;
attaching a microelectronic device to the plurality of microelectronic device attachment bond pads;
forming a mold chase having a mold body and at least one projection extending from the mold body, wherein the at least one projection includes at least one sidewall and a contact surface;
contacting the at least one mold chase projection contact surface to a respective microelectronic substrate interconnection bond pad;
disposing a mold material between the microelectronic substrate and the mold chase; and
removing the mold chase to form at least one interconnection via extending from a top surface of the mold material to a respective microelectronic substrate interconnection bond pad; and
filling the at least one interconnection via with a conductive material to form at least one through-mold interconnection;

and
attaching a second package to the first package, wherein an electrically connection is formed from the second package to the at least one through-mold interconnect of the first package.

44 . The method of claim 43 , further comprising curing the mold material prior the removing the mold chase.

45 . The method of claim 43 , wherein disposing the mold material comprises disposing the mold material between the microelectronic substrate and the mold chase to substantially encapsulate the microelectronic device and surrounds the at least one interconnection projection sidewall.

46 . The method of claim 43 , wherein forming the mold chase co

Assignees

• Karhade Omkar G
• Deshpande Nitin A
• Cetegen Edvin
• Li Eric J
• Mallik Debendra
• Ziadeh Bassam M
• Intel Corp

Inventors

• Karhade Omkar G
• Deshpande Nitin A
• Cetegen Edvin
• Li Eric J
• Mallik Debendra
• Ziadeh Bassam M

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title