Manufacturing method of semiconductor device

Patent metadata

Field	Value
Publication number	US-2016268130-A1
Application number	US-201514842191-A
Country	US
Kind code	A1
Filing date	Sep 1, 2015
Priority date	Mar 12, 2015
Publication date	Sep 15, 2016
Grant date	—

Abstract

According to one embodiment, a manufacturing method of a semiconductor device, comprising: forming a first nitride semiconductor layer on a substrate using a first temperature; decreasing a substrate temperature to a second temperature lower than the first temperature, after the forming the first nitride semiconductor layer; forming a second nitride semiconductor layer on the first nitride semiconductor layer using the second temperature; increasing the substrate temperature to a third temperature higher than the first temperature, after the forming the second nitride semiconductor layer; and forming a third nitride semiconductor layer on the second nitride semiconductor layer using the third temperature.

First claim

What is claimed is:

1 . A manufacturing method of a semiconductor device, comprising:
forming a first nitride semiconductor layer on a substrate using a first temperature; decreasing a substrate temperature to a second temperature lower than the first temperature, after the forming the first nitride semiconductor layer; forming a second nitride semiconductor layer on the first nitride semiconductor layer using the second temperature, the second nitride semiconductor layer formed of a material identical to a material of the first nitride semiconductor layer; increasing the substrate temperature to a third temperature higher than the first temperature, after the forming the second nitride semiconductor layer; and forming a third nitride semiconductor layer on the second nitride semiconductor layer using the third temperature, the third nitride semiconductor layer formed of a material identical to the material of the first nitride semiconductor layer.

2 . The method of claim 1 , further comprising:
forming a fourth semiconductor layer on the third nitride semiconductor layer, the fourth semiconductor layer formed of a material different from the material of the first nitride semiconductor layer.

3 . The method of claim 2 , wherein the fourth semiconductor layer is a nitride semiconductor layer.

4 . The method of claim 2 , wherein the forming the fourth semiconductor layer is performed using the third temperature.

5 . The method of claim 2 , wherein the forming the fourth semiconductor layer is performed using a fourth temperature higher than the first temperature and lower than the third temperature.

6 . The method of claim 1 , wherein a difference between the second temperature and the third temperature is larger than a difference between the first temperature and the second temperature.

7 . The method of claim 1 , wherein
the first temperature is 500° C. to 900° C., the second temperature is 300° C. to 650° C., and the third temperature is 750° C. to 1050° C.

8 . The method of claim 5 , wherein
the first temperature is 500° C. to 900° C., the second temperature is 300° C. to 650° C., the third temperature is 750° C. to 1100° C., and the fourth temperature is 750° C. to 1050° C.

9 . The method of claim 1 , wherein a difference between the first temperature and the second temperature is 45° C. to 227° C.

10 . The method of claim 1 , wherein a difference between the second temperature and the third temperature is 91° C. to 340° C.

11 . The method of claim 1 , wherein
in the decreasing, tensile strain of 0.01% to 0.05% is generated in the first nitride semiconductor layer, and in the increasing, compressive strain of 0.02% to 0.075% is generated in the second nitride semiconductor layer.

12 . The method of claim 1 , wherein
the first nitride semiconductor layer has a thickness of 10 nm to 200 nm, the second nitride semiconductor layer has a thickness of 20 nm to 200 nm, and the third nitride semiconductor layer has a thickness of 50 nm to 300 nm.

13 . The method of claim 1 , wherein the first nitride semiconductor layer has a thickness smaller than a thickness of the second nitride semiconductor layer.

14 . The method of claim 2 , wherein the fourth semiconductor layer has a lattice constant smaller than a lattice constant of the first nitride semiconductor layer.

15 . The method of claim 2 , wherein
the substrate is formed of a silicon substrate, the first nitride semiconductor layer is formed of aluminum nitride, and the fourth semiconductor layer is formed of gallium nitride.

16 . The method of claim 1 , wherein the forming the first to third nitride semiconductor layers are performed by using MOCVD (Metal Organic Chemical Vapor Deposition).

17 . The method of claim 1 , wherein a difference between the first temperature and the second temperature is set to cause lattice relaxation in the second nitride semiconductor layer.

18 . The method of claim 1 , wherein a difference between the third temperature and the first temperature is set to cause compressive stress in the third nitride semiconductor layer.

19 . A manufacturing method of a semiconductor device, comprising:
forming a first nitride semiconductor layer on a substrate such that tensile stress is generated in the first nitride semiconductor layer; forming a second nitride semiconductor layer on the first nitride semiconductor layer such that lattices are relaxed in the second nitride semiconductor layer, the second nitride semiconductor layer formed of a material identical to a material of the first nitride semiconductor layer; and forming a third nitride semiconductor layer on the second nitride semiconductor layer such that compressive stress is generated in the third nitride semiconductor layer, the third nitride semiconductor layer formed of a material identical to the material of the second nitride semiconductor layer.

20 . The method of claim 19 , further comprising:
forming a fourth semiconductor layer on the third nitride semiconductor layer such that compressive stress is generated in the fourth semiconductor layer, the fourth semiconductor layer formed of a material different from the material of the first nitride semiconductor layer.

Assignees

• Toshiba Kk

Inventors

• Sugiyama Naoharu
• Isobe Yasuhiro
• Hung Hung
• Yoshioka Akira

Classifications

• H10P14/3822

  Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing · CPC title

• H10P14/3416

  Nitrides · CPC title

• H10P14/3251

  consisting of three or more layers · CPC title

• H10P14/3216

  Nitrides · CPC title

• H10P14/2926

  Crystal orientations · CPC title