Load-tracking frequency compensation in a voltage regulator

Patent metadata

Field	Value
Publication number	US-2016266591-A1
Application number	US-201514656398-A
Country	US
Kind code	A1
Filing date	Mar 12, 2015
Priority date	Mar 12, 2015
Publication date	Sep 15, 2016
Grant date	—

Abstract

Disclosed is circuitry having an input stage and an output stage. A first compensation network may be connected to the input and output stages, and configured to split a pole at the input stage and a pole at the output stage. A second compensation network may be connected to the input and output stage. The second compensation network may be configured to suppress peaking of a gain of the circuit at frequencies near the pole at the output stage.

First claim

We claim the following:

1 . A circuit comprising:
an input stage having an input configured to connect to an input voltage; an output stage having an output, the output stage configured to produce an output voltage on the output; a first compensation network connected to the input stage and the output stage and configured to split a first pole at an output of the input stage and a second pole at the output of the output stage; and a second compensation network connected to the input stage and the output stage, the second compensation network configured to suppress peaking of a gain of the circuit at frequencies near the second pole.

2 . The circuit of claim 1 , wherein the second compensation network is configured to establish a pole at the output of the output stage to suppress gain peaking of the circuit at frequencies near the second pole.

3 . The circuit of claim 2 , further comprising a feedback loop connected to the input stage and to the output stage, wherein the second compensation network is configured to establish the pole in the feedback loop.

4 . The circuit of claim 1 , further comprising a feedback loop connected to the input stage and to the output stage, the second compensation network further configured to stabilize the feedback loop at frequencies near the second pole in response to changes in a loading condition at the output of the output stage.

5 . The circuit of claim 1 , wherein the second compensation network is configured to establish a zero at a frequency that varies with the loading condition at the output of the output stage.

6 . The circuit of claim 5 , further comprising a signal source configured to produce a signal indicative of a loading condition at the output of the output stage.

7 . The circuit of claim 5 , wherein a signal at the output of the input stage is representative of the loading condition at the output of the output stage.

8 . The circuit of claim 1 , wherein the input stage includes a cascode stage and the first compensation network comprises a capacitor connected to the cascode stage.

9 . The circuit of claim 8 , wherein the first compensation network does not include a resistive element.

10 . The circuit of claim 1 , wherein the second compensation network comprises a resistive element and capacitor.

11 . The circuit of claim 10 , wherein the resistive element is a MOSFET device.

12 . The circuit of claim 1 , wherein the input voltage is a reference voltage and the circuit is configured to regulate an output voltage on the output of the output stage based on the reference voltage.

13 . A circuit comprising:
a differential amplifier having a first input, a second input, and an output, the first input configured to connect to an external voltage source; a pass device having a control terminal and an output terminal, the control terminal in electrical communication with the output of the differential amplifier; a feedback network connected between the output terminal of the pass device and the second input of the differential amplifier; a first compensation network connected between the output terminal of the pass device and an internal node of the differential amplifier; and a second compensation network comprising a variable RC network configured to suppress peaking of a gain of the circuit at frequencies near a pole at the output terminal of the pass device in response to changes in a loading condition at the output terminal of the pass device.

14 . The circuit of claim 13 , wherein the first compensation network comprises a capacitor configured to provide Miller compensation.

15 . The circuit of claim 13 , wherein the differential amplifier comprises a cascode stage, wherein the first compensation network is connected to a node in the cascode stage.

16 . The circuit of claim 15 , wherein the first compensation network comprises a capacitor connected between the output terminal of the pass device and the node in the cascode stage of the differential amplifier.

17 . The circuit of claim 13 , wherein the feedback network comprises a resistor divider network connected to the output terminal of the pass device, wherein the first compensation network is connected to a node in the resistor divider network.

18 . The circuit of claim 13 , wherein the variable RC network of the second compensation network comprises a MOSFET device connected in series with a capacitor, the output of the differential amplifier in electrical communication with the control terminals of both the MOSFET device and the pass device.

19 . The circuit of claim 18 , further comprising a buffer circuit having an input connected to the output of the differential amplifier and the capacitor of the variable RC network, the buffer circuit further having an output connected to the control terminals of both the MOSFET device and the pass device.

20 . A circuit comprising:
first means for producing an output signal at an output node of the circuit; second means for producing an error signal based on a reference signal and the output signal at the output node of the circuit; third means for stabilizing operation of the circuit by splitting a first pole at a node in the circuit where the error signal is produced and a second pole at the output node of the circuit; and fourth means for suppressing gain peaking at frequencies above a unity gain frequency of the circuit by establishing a third pole at the output node of the circuit.

21 . The circuit of claim 20 , further comprising:
means for establishing a zero at the output node of the circuit; and means for changing a location of the zero in response to a loading condition at the output node of the circuit to compensate for the second pole the output node of the circuit.

22 . The circuit of claim 21 , wherein a location of the second pole changes as the loading condition at the output node changes, wherein changing the location of the zero includes tracking movement of the second pole.

23 . The circuit of claim 21 , wherein means for changing the location of the zero includes setting a complex impedance of an RC network in the circuit using a signal representative of the loading condition at the output node of the circuit.

24 . The circuit of claim 20 , further comprising means for producing a feedback signal using a resistor divider network connected to the output node of the circuit and comparing the feedback signal with the reference signal to produce the error signal.

25 . A method in a circuit comprising:
producing an output signal at an output node of the circuit; producing an error signal based on a reference signal and the output signal at the output node of the circuit; regulating the output signal at the output node of the circuit using the error signal; stabilizing operation of the circuit by splitting a first pole at a node in the circuit where the error signal is produced and a second pole at the output node of the circuit; and suppressing gain peaking at frequencies above a unity gain frequency of the circuit by establishing a third pole at the output node of the circuit.

26 . The method of claim 25 , further comprising:
establishing a zero at the output node of the circuit; and changing a location of the zero in response to a loading condition at the output node of the circuit to compensate for the second pole the output node of the circuit.

Assignees

• Qualcomm Inc

Inventors

• Hua Jun
• Mirea Iulian

Classifications

• G05F1/46

  wherein the variable actually regulated by the final control device is DC (G05F1/625 takes precedence) · CPC title

• G05F1/56

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title

• G05F3/262

  using field-effect transistors only · CPC title

• G05F1/575

  characterised by the feedback circuit · CPC title

• G05F1/445 Primary

  being transistors in series with the load · CPC title