Pattern formation method, control device, and semiconductor device manufacture method

US2016259240A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016259240-A1
Application numberUS-201514848075-A
CountryUS
Kind codeA1
Filing dateSep 8, 2015
Priority dateMar 4, 2015
Publication dateSep 8, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

In a pattern formation method according to an embodiment, a resist pattern is formed on a first film formed on a substrate. In the process for forming the resist pattern, the resist pattern includes a first pattern including a defect in a predetermined region on the first film. Next, a second film is accumulated on the first pattern in the predetermined region. Furthermore, a second pattern is formed in the first film with the resist pattern and the second film. Then, a third pattern is formed in the predetermined region on the first film.

First claim

Opening claim text (preview).

What is claimed is: 1 . A pattern formation method comprising: forming a resist pattern on a first film formed on a substrate, the resist pattern including a first pattern in a predetermined region on the first film, the first pattern including a pattern defect; accumulating a second film in the predetermined region on the first pattern; forming the first film into a second pattern in accordance with the resist pattern and the second film; and forming a third pattern in the predetermined region on the first film. 2 . The pattern formation method according to claim 1 , wherein the resist pattern includes a fourth pattern in a third region and the fourth pattern is formed by a film material having an amount larger than a desired amount; and a position on which the second film is to be accumulated is set in accordance with a position and a size of the first pattern and a position and a size of the fourth pattern. 3 . The pattern formation method according to claim 1 , further comprising: removing the resist pattern and the second film, wherein the third pattern is formed after the removal of the resist pattern and the second film. 4 . The pattern formation method according to claim 1 , further comprising: etching a layer lower than the first film after the formation of the third pattern, using the first film as a hard mask after the formation of the third pattern. 5 . The pattern formation method according to claim 1 , wherein protectant is dropped on the predetermined region in an ink-jet manner, and the second film is accumulated by the dropping. 6 . The pattern formation method according to claim 1 , wherein a charged particle beam reacts with a process gas and the second film is accumulated on the first pattern by the reaction. 7 . The pattern formation method according to claim 1 , wherein the resist pattern includes a fourth pattern in a third region, and the fourth pattern is formed by a film material having an amount larger than a desired amount; and the amount of the second film is set in accordance with a position and a size of the first pattern and a position and a size of the fourth pattern. 8 . The pattern formation method according to claim 1 , further comprising: setting a center of an accumulation position of the second film at a position such that the first pattern is entirely covered and the resist pattern is covered as widely as possible, the accumulation position being a position on which the second film is to be accumulated. 9 . The pattern formation method according to claim 7 , further comprising: setting a center of an accumulation position of the second film at a position such that the first pattern is entirely covered and the fourth pattern and the resist pattern are covered as widely as possible, the accumulation position being a position on which the second film is to be accumulated. 10 . The pattern formation method according to claim 5 , further comprising: setting a position on which the second film is to be accumulated in accordance with a minimum size to which the protectant is accumulated in the ink-jet manner and a minimum size of a circular region necessary to encompass a defect part in the first pattern. 11 . The pattern formation method according to claim 3 , wherein the first film in the predetermined region is processed, and the third pattern is formed by the process. 12 . The pattern formation method according to claim 11 , wherein the third pattern is formed with a charged particle beam correction apparatus. 13 . The pattern formation method according to claim 5 , wherein the protectant is a resist. 14 . The pattern formation method according to claim 6 , wherein the second film is a metal film or a metal-oxide film. 15 . A control device comprising: a defect region extraction unit that extracts first positional information indicating a position of a first pattern including a defect in a substrate pattern, the first pattern being formed on a first film on a substrate; a position setting unit that sets an accumulation position on which a second film is to be accumulated on the substrate in accordance with the first positional information; and an instruction output unit that outputs an instruction to accumulate the second film on the accumulation position. 16 . The control device according to claim 15 , wherein the defect region extraction unit further extracts second positional information indicating a position of a second pattern formed by a film material having an amount larger than a desired amount from the substrate pattern, and the position setting unit sets the accumulation position in accordance with a position and a size of the first pattern and a position and a size of the second pattern. 17 . The control device according to claim 15 , wherein the defect region extraction unit further extracts second positional information indicating a position of a second pattern formed by a film material having an amount larger than a desired amount from the substrate pattern, and the position setting unit sets an amount of the second film in accordance with a position and a size of the first pattern and a position and a size of the second pattern. 18 . The control device according to claim 15 , wherein the position setting unit sets a center of the accumulation position of the second film at a position such that the first pattern is entirely covered and the substrate pattern is covered as widely as possible. 19 . The control device according to claim 15 , wherein the position setting unit sets a center of the accumulation position of the second film at a position such that the first pattern is entirely covered and the second pattern and the substrate pattern are covered as widely as possible. 20 . A semiconductor device manufacture method, the method comprising: forming a first resist pattern on a first film formed on a first substrate, the first resist pattern including a first pattern in a predetermined region on the first film, the first pattern including a pattern defect; accumulating a second film in the predetermined region on the first pattern; forming the first film into a second pattern in accordance with the resist pattern and the second film; forming a third pattern in the predetermined region on the first film; forming a second resist pattern on a third film formed on a second substrate with the first substrate, the first substrate on which the third pattern is formed; and forming a fourth pattern in the third film with the second resist pattern.

Assignees

Inventors

Classifications

  • Etching · CPC title

  • by charged particle beam [CPB], e.g. focused ion beam · CPC title

  • G03F1/72Primary

    Repair or correction of mask defects · CPC title

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What does patent US2016259240A1 cover?
In a pattern formation method according to an embodiment, a resist pattern is formed on a first film formed on a substrate. In the process for forming the resist pattern, the resist pattern includes a first pattern including a defect in a predetermined region on the first film. Next, a second film is accumulated on the first pattern in the predetermined region. Furthermore, a second pattern is …
Who is the assignee on this patent?
Toshiba Kk
What technology area does this patent fall under?
Primary CPC classification G03F1/72. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Sep 08 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).