Method for modifying a stress level of a semiconductor device having transistor channel stages

Patent metadata

Field	Value
Publication number	US-2016254362-A1
Application number	US-201615049468-A
Country	US
Kind code	A1
Filing date	Feb 22, 2016
Priority date	Feb 24, 2015
Publication date	Sep 1, 2016
Grant date	—

Abstract

A Method for modifying the strain state of a semiconducting structure, comprising steps to:
a) provide at least one first semiconducting structure on a substrate, formed from a semiconducting stack comprising an alternation of elements based on the first semiconducting material and elements based on the second semiconducting material, then b) remove portions of the second semiconducting material from the first structure so as to form empty spaces, c) fill in the empty spaces with a dielectric material, d) form a straining zone on the first structure, based on a first strained material, e) perform appropriate thermal annealing so as to make the dielectric material creep or relax, and cause a change in the strain state of elements based on the first semiconducting material in the structure.

First claim

1 . A method of making a microelectronic device provided with at least one first transistor with a first channel structure formed from semiconducting elements located above each other, the method comprising steps to:
a) provide at least one first semiconducting structure on a substrate, formed from a semiconducting stack comprising an alternation of elements based on at least one first semiconducting material and elements based on at least one second semiconducting material different from the first semiconducting material, then b) remove portions of the second semiconducting material from the first structure by selective etching, the removed portions of the second semiconducting material forming one or several empty spaces, c) fill in the empty spaces with a dielectric material, d) form a straining zone on the first structure, based on a first strained material with an intrinsic strain, e) perform appropriate thermal annealing so as to make the dielectric material creep, and cause a change in the strain state of elements based on the first semiconducting material in the first structure.

2 . The method according to claim 1 , wherein the microelectronic device is provided with at least one second transistor with a second channel structure formed from semiconducting elements located above each other, at least one second semiconducting structure formed in the semiconducting stack and comprising an alternation of elements based on at least one first semiconducting material and elements based on at least one second semiconducting material different from the first semiconducting material provided in step a),
step d) comprising steps to:
deposit the first strained material on the first structure and on the second structure, then
remove the first strained material from the second structure.

3 . The method according to claim 2 , also comprising steps to:
form a straining zone on the second structure based on a second strained material with an intrinsic strain opposite the strain in the first strained material.

4 . The method according to claim 2 , wherein the first structure and the second structure provided in step a) are attached to each other by means of at least one anchor block, the anchor block being removed before step e).

5 . The method according to claim 4 , wherein the anchor block is removed after step d) by etching making use of the straining zone as a protective stencil for this etching.

6 . The method according to claim 1 , wherein the substrate provided in step a) is a strained semiconducting on insulator type substrate provided with a strained surface semiconducting layer, the change in the strain state in step e) being relaxation of the elements based on the first semiconducting material.

7 . The method according to claim 1 , wherein the substrate provided in step a) is a strained semiconducting on insulator type substrate provided with a relaxed surface semiconducting layer, the change in the strain state in step e) being an increase in a strain state induced by the straining zone in the elements based on the first semiconducting material.

8 . The method according to claim 1 , wherein the dielectric material is based on SiO 2 or doped silicon oxide.

9 . The method according to claim 1 , wherein the first semiconducting material is Si while the second semiconducting material is Si 1-y Ge y where y>0 or in which the first semiconducting material is Si 1-x Ge x where x>0, while the second semiconducting material is Si.

Assignees

• Commissariat Energie Atomique

Inventors

• Maitrejean Sylvain
• Augendre Emmanuel
• Barbe Jean-Charles
• Mathieu Benoit
• Morand Yves

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title

• H10D64/015

  removing at least parts of gate spacers, e.g. disposable spacers · CPC title