Method of manufacturing a semiconductor device

Patent metadata

Field	Value
Publication number	US-2016254264-A1
Application number	US-201615147951-A
Country	US
Kind code	A1
Filing date	May 6, 2016
Priority date	Mar 19, 2012
Publication date	Sep 1, 2016
Grant date	—

Abstract

A method of manufacturing a semiconductor device includes preparing a light ion source, a first mask and a second mask. A side of a first region on a top surface of a semiconductor substrate is shielded by using the first mask. The top surface, with the side of the first region thereon being shielded with the first mask, is irradiated with light ions by operating the light ion source to introduce lattice defects at a specified depth on a side of a second region on the top surface. A side of the second region on a bottom surface of the semiconductor substrate is shielded by using the second mask. The bottom surface, with the side of the second region thereon being shielded with the second mask, is irradiated with light ions by operating the light ion source to introduce lattice defects at a specified depth on the side of the first region on the bottom surface.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device having a first semiconductor element provided in a first region in a semiconductor substrate, and a second semiconductor element provided in a second region in the semiconductor substrate, the method comprising:
preparing a light ion source, a first mask and a second mask; shielding a side of the first region on a top surface of the semiconductor substrate by using the first mask; irradiating the top surface of the semiconductor substrate, the side of the first region thereon being shielded with the first mask, with light ions by operating the light ion source to introduce lattice defects at a specified depth on a side of the second region on the top surface of the semiconductor substrate; shielding the side of the second region on a bottom surface of the semiconductor substrate by using the second mask; and irradiating the bottom surface of the semiconductor substrate, the side of the second region thereon being shielded with the second mask, with light ions by operating the light ion source to introduce lattice defects at a specified depth on the side of the first region on the bottom surface of the semiconductor substrate.

2 . The method of manufacturing a semiconductor device as claimed in claim 1 , wherein in irradiating the top surface of the semiconductor substrate, a carrier lifetime on the side of the top surface element structure of the second semiconductor element is made shorter than a carrier lifetime on the side of the top surface element structure of the first semiconductor element.

3 . The method of manufacturing a semiconductor device as claimed in claim 1 , wherein in irradiating the bottom surface of the semiconductor substrate, a carrier lifetime on the side of the bottom surface element structure of the first semiconductor element is made shorter than a carrier lifetime on the side of the bottom surface element structure of the second semiconductor element.

4 . The method of manufacturing a semiconductor device as claimed in claim 2 , wherein the semiconductor substrate is a semiconductor substrate of a first conduction type which is provided with an insulated gate structure as the top surface element structure of the first semiconductor element, the insulated gate structure including a base region of a second conduction type, an emitter region of the first conduction type and a gate electrode, and is provided with an anode region of the second conduction type as the top surface element structure of the second semiconductor element, and
in irradiating the top surface of the semiconductor substrate, the carrier lifetime on the side of the anode region is made shorter than the carrier lifetime on the side of the emitter region.

5 . The method of manufacturing a semiconductor device as claimed in claim 4 , wherein the semiconductor substrate of the first conduction type is provided with a cathode region of the first conduction type as the bottom surface element structure of the second semiconductor element, and
in irradiating the top surface of the semiconductor substrate, the carrier lifetime on the side of the anode region is made shorter than the carrier lifetime on the side of the cathode region.

6 . The method of manufacturing a semiconductor device as claimed in claim 3 , wherein the semiconductor substrate of the first conduction type is provided with a collector region of the second conduction type as the bottom surface element structure of the first semiconductor element, and is provided with a cathode region of the first conduction type as the bottom surface element structure of the second semiconductor element, and
in irradiating the bottom surface of the semiconductor substrate, the carrier lifetime on the side of the collector region is made shorter than the carrier lifetime on the side of the cathode region.

7 . The method of manufacturing a semiconductor device as claimed in claim 6 , wherein the semiconductor substrate of the first conduction type is provided with the insulated gate structure as the top surface element structure of the first semiconductor element, the insulated gate structure including a base region of a second conduction type, an emitter region of the first conduction type and a gate electrode, and
in irradiating the bottom surface of the semiconductor substrate, the carrier lifetime on the side of the collector region is made shorter than the carrier lifetime on the side of the emitter region.

8 . The method of manufacturing a semiconductor device as claimed in claim 1 , wherein in each of irradiating the top surface of the semiconductor substrate and irradiating the bottom surface of the semiconductor substrate, the irradiation is carried out with a particle beam of one of protons and helium ions.

Assignees

• Fuji Electric Co Ltd

Inventors

• Mizushima Tomonori

Classifications

• H10P30/22

  using masks · CPC title

• H10D62/53

  the imperfections being within the semiconductor body · CPC title

• H10D12/481

  having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs · CPC title

• H10D12/441

  Vertical IGBTs · CPC title

• H10D12/211

  Gated diodes · CPC title