Compound semiconductor structure

US2016254147A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016254147-A1
Application numberUS-201615149913-A
CountryUS
Kind codeA1
Filing dateMay 9, 2016
Priority dateAug 27, 2013
Publication dateSep 1, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A method for fabricating semiconductor structure comprises the steps of providing a substrate including a first crystalline semiconductor material, patterning an opening in a dielectric layer above the substrate, the opening having a bottom, forming a crystalline interlayer on the substrate at least partially covering the bottom, and growing a second crystalline semiconductor material on the crystalline interlayer thereby at least partially filling the opening. The crystalline semiconductor materials are lattice mismatched, and the crystalline interlayer comprises an oxygen compound.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method for fabricating semiconductor structure comprising: providing a substrate including a first crystalline semiconductor material; patterning an opening in a dielectric layer above the substrate, the opening having a bottom; forming a crystalline interlayer on the substrate at least partially covering the bottom; and growing a second crystalline semiconductor material on the crystalline interlayer thereby at least partially filling the opening; wherein: the first crystalline semiconductor material and the second crystalline semiconductor material are lattice mismatched; and the crystalline interlayer comprises an oxygen compound. 2 . The method of claim 1 , further comprising forming the dielectric layer on the substrate. 3 . The method of claim 1 , further comprising forming the dielectric layer on the crystalline interlayer. 4 . The method of claim 1 , wherein the opening is patterned in the dielectric layer thereby forming sidewalls of the opening. 5 . The method of claim 1 , wherein the step of patterning the opening is performed after forming the crystalline interlayer. 6 . The method of claim 1 , wherein growing the second crystalline semiconductor material on the crystalline interlayer comprises forming islands of said second crystalline semiconductor material on the crystalline interlayer. 7 . The method of claim 6 , further comprising coalescing the islands thereby forming an epitaxial film. 8 . The method of claim 1 , wherein growing the second crystalline semiconductor material on the crystalline interlayer comprises forming a single island of said second crystalline semiconductor material on the crystalline interlayer in the opening. 9 . The method of claim 1 , further comprising overgrowing the opening with the second crystalline semiconductor material thereby filling the opening. 10 . The method of claim 9 , further comprising, after filling the opening with the second crystalline semiconductor material, planarizing overgrown second crystalline semiconductor material. 11 . The method of claim 1 , further comprising processing the second crystalline semiconductor material for fabricating electronic or optical devices.

Assignees

Inventors

Classifications

  • Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth · CPC title

  • Arsenides · CPC title

  • characterised by the chemical composition · CPC title

  • being insulating materials · CPC title

  • Silicon, silicon germanium or germanium · CPC title

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What does patent US2016254147A1 cover?
A method for fabricating semiconductor structure comprises the steps of providing a substrate including a first crystalline semiconductor material, patterning an opening in a dielectric layer above the substrate, the opening having a bottom, forming a crystalline interlayer on the substrate at least partially covering the bottom, and growing a second crystalline semiconductor material on the cr…
Who is the assignee on this patent?
Globalfoundries Inc
What technology area does this patent fall under?
Primary CPC classification H10P14/2905. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Sep 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).