Test-per-clock based on dynamically-partitioned reconfigurable scan chains

Patent metadata

Field	Value
Publication number	US-2016252573-A1
Application number	US-201615150147-A
Country	US
Kind code	A1
Filing date	May 9, 2016
Priority date	Jun 17, 2013
Publication date	Sep 1, 2016
Grant date	—

Abstract

Aspects of the invention relate to a test-per-clock scheme based on dynamically-partitioned reconfigurable scan chains. Every clock cycle, scan chains configured by a control signal to operate in a shifting-launching mode shift in test stimuli one bit and immediately applies the newly formed test pattern to the circuit-under-test; and scan chains configured by the control signal to operate in a capturing-compacting-shifting mode shift out one bit of previously compacted test response data while compacting remaining bits of the previously compacted test response data with a currently-captured test response to form currently compacted test response data. A large number of scan chains may be configured by the control signal to work in a mission mode. After a predetermined number of clock cycles, a different control signal may be applied to reconfigure and partition the scan chains for applying different test stimuli.

First claim

1 .- 16 . (canceled)

17 . A method, comprising:
shifting test stimuli into a first portion of a plurality of scan chains in a circuit one bit per scan chain to form a new test pattern; applying the new test pattern to the circuit; shifting out previously compacted test response data stored in a second portion of the plurality of scan chains one bit per scan chain; compacting a test response corresponding to the new test pattern with the previously compacted test response data to generate newly compacted test response data in the second portion of the plurality of scan chains; and repeating the above operations for a predetermined number of times.

18 . The method recited in claim 17 , further comprising:
applying a control signal to configure some scan chains in the plurality of scan chains to operate in a shifting-launching mode as the first portion of the plurality of scan chains, some other scan chains in the plurality of scan chains to operate in a capturing-compacting-shifting mode as the second portion of the plurality of scan chains, rest of the plurality of scan chains to operate in a mission mode as the third portion of the plurality of can chains.

19 . The method recited in claim 17 , wherein the control signal is stored in a register in the circuit.

20 . The method recited in claim 17 , wherein parallel outputs of the second portion of the plurality of scan chains are blocked from driving the circuit.

Assignees

• Mentor Graphics Corp

Inventors

• Rajski Janusz
• Solecki Jedrzej
• Tyszer Jerzy
• Mrugalski Grzegorz

Classifications

• G01R31/31704

  Design for test; Design verification (concerning scan tests G01R31/318583; computer-aided design G06F30/00) · CPC title

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/318575

  Power distribution; Power saving · CPC title

• G01R31/318555 Primary

  Control logic · CPC title

• G01R31/318547 Primary

  Data generators or compressors · CPC title