Fabric multipathing based on dynamic latency-based calculations

Patent metadata

Field	Value
Publication number	US-2016248577-A1
Application number	US-201615141612-A
Country	US
Kind code	A1
Filing date	Apr 28, 2016
Priority date	Jul 18, 2013
Publication date	Aug 25, 2016
Grant date	—

Abstract

In one embodiment, a computer program product includes a computer readable storage medium having program instructions embodied therewith, the program instructions being executable by a processor to cause the processor to determine a lowest latency LAG port for each LAG in any path of a plurality of paths connecting a first device with a second device, and discover a configuration of a network fabric connecting the first device to the second device after determining the lowest latency LAG port for each LAG therein. The network fabric includes a plurality of devices interconnected with LAGs. Moreover, the embodied program instructions are executable by the processor to perform clock synchronization for each path of the plurality of paths and determine a latency for each path of the plurality of paths based on the clock synchronization and the lowest latency LAG port for each LAG included in the plurality of paths.

First claim

What is claimed is:

1 . A computer program product comprising a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the embodied program instructions being executable by a processor to cause the processor to:
synchronize, by the processor, clocks of two intermediate devices across a plurality of link aggregation (LAG) ports 1 to N therebetween, wherein N is at least 2, and wherein the clock synchronization is performed independently across each of the LAG ports; determine, by the processor, a latency for each LAG port based on information derived from synchronizing the clocks of the two intermediate devices; store, by the processor, the latency for each LAG port to a LAG structure along with an identifier of a corresponding LAG port and mark a LAG port having a lowest latency; discover, by the processor, a configuration of a network fabric after determining the latency for each LAG port; synchronize, by the processor, a first clock of a first device and a second clock of a second device across a plurality of paths connecting the first device with the second device through a network fabric, wherein the first clock and the second clock are synchronized independently across the paths connecting the first device with the second device, including independently across each LAG port of at least one LAG included in at least one of the paths connecting the first device with the second device; and determine, by the processor, a latency for each path of the plurality of paths connecting the first device with the second device in the network fabric based on information derived from synchronizing the first and second clocks and the latency for LAG ports included in the plurality of paths.

2 . The computer program product as recited in claim 1 , wherein the embodied program instructions are further executable by the processor to cause the processor to:
store, by the processor, the latency for each path of the plurality of paths connecting the first device with the second device in the network fabric to an equal cost multi-path (ECMP) structure along with an identifier for each path of the plurality of paths connecting the first device with the second device in the network fabric; and sort, by the processor, the plurality of paths according to each path's latency and marking a path having a lowest latency.

3 . The computer program product as recited in claim 1 , wherein the clock synchronization is performed via Institute of Electrical and Electronics Engineers (IEEE) standard 1588-2002 or 1588-2008.

4 . The computer program product as recited in claim 1 , wherein the embodied program instructions executable to cause the processor to synchronize the first clock and the second clock further causes the processor to:
determine, by the processor, an offset between the first clock and the second clock across each path of the plurality of paths connecting the first device with the second device in the network fabric; and determine, by the processor, a transit delay for each path of the plurality of paths connecting the first device with the second device in the network fabric, wherein the latency for each path of the plurality of paths connecting the first device with the second device in the network fabric is based on the transit delay for the path.

5 . The computer program product as recited in claim 4 , wherein the first clock acts as a master clock in the clock synchronization.

6 . The computer program product as recited in claim 4 , wherein a clock source having a stratum of zero or one acts as a master clock in the clock synchronization.

7 . The computer program product as recited in claim 4 , wherein the offset between the first clock and the second clock is determined for each path of the plurality of paths connecting the first device with the second device in the network fabric by:
causing, by the processor, the first device to send a synchronization message to the second device at a first time, T(M)(1), across each path of the plurality of paths connecting the first device with the second device in the network fabric; determining, by the processor, a second time, T(S)(2), at which each synchronization message is received at the second device across each path of the plurality of paths connecting the first device with the second device in the network fabric; and calculating, by the processor, a difference between the second time and the first time, such that Offset=T(S)(2)−T(M)(1), for each path of the plurality of paths connecting the first device with the second device in the network fabric.

8 . The computer program product as recited in claim 7 , wherein the offset between the first clock and the second clock is determined periodically for each path connecting the first device with the second device in the network fabric by:
causing, by the processor, the first device to send a follow-up message to the second device at a third time, T(M)(3), across each path of the plurality of paths connecting the first device with the second device in the network fabric; determining, by the processor, a fourth time, T(S)(4), at which each follow-up message is received at the second device across each path of the plurality of paths connecting the first device with the second device in the network fabric; and calculating, by the processor, a difference between the fourth time and the third time, such that Offset=T(S)(4)−T(M)(3), for each path of the plurality of paths connecting the first device with the second device in the network fabric.

9 . The computer program product as recited in claim 1 , wherein the latency for each path of the plurality of paths connecting the first device with the second device in the network fabric is determined every tenth of a second.

10 . The computer program product as recited in claim 1 , wherein the embodied program instructions are further executable by the processor to cause the processor to:
receive, by the processor, first and second packets; determine, by the processor, whether the first and second packets demand low latency service; forward, by the processor, the first packet using the path having the lowest latency in response to a determination that the first packet demands low latency service; and choose, by the processor, a path to forward the second packet other than the path marked as having the lowest latency in response to a determination that the second packet does not demand low latency service.

11 . A computer program product comprising a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the embodied program instructions being executable by a processor to cause the processor to:
determine, by the processor, a lowest latency link aggregation (LAG) port for each LAG in any path of a plurality of paths connecting a first device with a second device; discover, by the processor, a configuration of a network fabric connecting the first device to the second device after determining the lowest latency LAG port for each LAG therein, wherein the network fabric comprises a plurality of devices interconnected with LAGs; perform, by the processor, clock synchronization for each path of the plurality of paths; and determine, by the processor, a latency for each path of the plurality of paths based on the clock synchronization and the lowest latency LAG port for each LAG included in the plurality of paths.

12 . The computer program product as recited in claim 11 , wherein the embodied program instruction

Assignees

• IBM

Inventors

• Ilyas Talha J
• Kamble Keshav G
• Pandey Vijoy A

Classifications

• H04L43/0852 Primary

  Delays · CPC title

• H04L7/02 Primary

  Speed or phase control by the received code signals, the signals containing no special synchronisation information {(H04L7/0075 takes precedence)} · CPC title

• H04L7/0054

  Detection of the synchronisation error by features other than the received signal transition (by means of signal transition H04L7/033) · CPC title

• H04L45/121

  by minimising delays · CPC title

• H04L45/20

  Hop count for routing purposes, e.g. TTL · CPC title