Semiconductor device, layout design and method for manufacturing a semiconductor device

Patent metadata

Field	Value
Publication number	US-2016240472-A1
Application number	US-201514621067-A
Country	US
Kind code	A1
Filing date	Feb 12, 2015
Priority date	Feb 12, 2015
Publication date	Aug 18, 2016
Grant date	—

Abstract

A semiconductor device includes a first interconnect structure. The first interconnect structure includes a first interconnect portion, a second interconnect portion and a third interconnect portion. The first interconnect portion has a width and a length. The second interconnect portion has a width less than the length of the first interconnect portion. The second interconnect portion is connected to the first interconnect portion. The third interconnect portion has a width less than the width of the second interconnect portion. The third interconnect portion is connected to the second interconnect portion.

First claim

1 . A semiconductor device comprising:
a first interconnect structure comprising:
a first interconnect portion having a width and a length;
a second interconnect portion having a width less than the length of the first interconnect portion, wherein the second interconnect portion is connected to the first interconnect portion; and
a third interconnect portion having a width less than the width of the second interconnect portion, wherein the third interconnect portion is connected to the second interconnect portion.

2 . The semiconductor device of claim 1 , wherein the width of the first interconnect portion is at least greater than six times a minimum design width of the first interconnect portion; and
wherein the width of the second interconnect portion is at least greater than 1.5 times the minimum design width of the first interconnect portion.

3 . The semiconductor device of claim 1 , wherein the second interconnect portion has a length that is at least greater than one-third of the width of the first interconnect portion.

4 . The semiconductor device of claim 1 , further comprising:
a first structure; and a second structure, wherein the first structure does not overlap the second structure, and wherein the first interconnect structure is over the first structure and the second structure, is connected to the first structure or the second structure.

5 . The semiconductor device of claim 1 , further comprising a second interconnect structure connected to the first interconnect structure.

6 . The semiconductor device of claim 5 , wherein the first interconnect structure and the second interconnect structure are located on a same interconnect layer.

7 . The semiconductor device of claim 6 , wherein the second interconnect structure comprises:
a fourth interconnect portion having a length, and a fifth interconnect portion having a width, wherein the fifth interconnect portion is connected to the third interconnect portion and the fourth interconnect portion, wherein the width of the fifth interconnect portion is less than the length of the fourth interconnect portion.

8 . The semiconductor device of claim 5 , wherein the first interconnect structure and the second interconnect structure are located on a different interconnect layer, and the first interconnect structure is connected to the second interconnect structure by at least one via.

9 . The semiconductor device of claim 1 , wherein the first interconnect portion, the second interconnect portion and the third interconnect portion are arranged in an L-shape, a T-shape or a comb shape.

10 . An integrated circuit designing system, comprising:
a non-transitory storage medium, the non-transitory storage medium configured to store a layout design of a semiconductor device and a set of instructions, the layout design comprising:
a first interconnect structure layout pattern associated with forming a first interconnect structure of the semiconductor device, wherein the first interconnect structure layout pattern comprises:
a first interconnect portion layout pattern associated with forming a first interconnect portion of the semiconductor device, wherein the first interconnect portion layout pattern has a width and a length;
a second interconnect portion layout pattern associated with forming a second interconnect portion of the semiconductor device, wherein the second interconnect portion layout pattern has a width that is less than the length of the first interconnect portion layout pattern, and wherein the second interconnect portion layout pattern is connected to the first interconnect portion layout pattern; and
a third interconnect portion layout pattern associated with forming a third interconnect portion of the semiconductor device, wherein the third interconnect portion layout pattern has a width less than the width of the second interconnect portion layout pattern, wherein the third interconnect portion layout pattern is connected to the second interconnect portion layout pattern;

wherein the set of instructions is for generating an integrated circuit layout based on an original circuit design and the layout design of the semiconductor device; and a hardware processor communicatively coupled with the non-transitory storage medium and configured to execute the set of instructions.

11 . The integrated circuit designing system of claim 10 , wherein the set of instructions is for generating that the width of the first interconnect portion layout pattern is at least greater than six times a minimum design width of the first interconnect portion layout pattern; and
wherein the set of instructions is for generating that the width of the second interconnect portion layout pattern is at least greater than 1.5 times the minimum design width of the first interconnect portion layout pattern.

12 . The integrated circuit designing system of claim 11 , wherein the set of instructions is for generating that the second interconnect portion layout pattern has a length that is at least greater than one-third of the width of the first interconnect portion layout pattern.

13 . The integrated circuit designing system of claim 10 , wherein the layout design further comprises a second interconnect structure layout pattern associated with forming a second interconnect structure of the semiconductor device, wherein the second interconnect structure layout pattern is connected to the first interconnect structure.

14 . The integrated circuit designing system of claim 13 , wherein the set of instructions is for generating that the second interconnect structure layout pattern comprises:
a fourth interconnect portion layout pattern associated with forming a fourth interconnect portion of the semiconductor device, wherein the fourth interconnect portion layout pattern has a length, and a fifth interconnect portion layout pattern associated with forming a fifth interconnect portion of the semiconductor device, wherein the fifth interconnect portion layout pattern has a width, wherein the fifth interconnect portion layout pattern is connected to the third interconnect portion layout pattern and the fourth interconnect portion layout pattern, wherein the width of the fifth interconnect portion layout pattern is less than the length of the fourth interconnect portion layout pattern.

15 . The integrated circuit designing system of claim 13 , wherein the set of instructions is for generating that the first interconnect structure layout pattern and the second interconnect structure layout pattern being located on a different interconnect layer, and wherein the set of instructions is for generating that the first interconnect structure layout pattern being connected to the second interconnect structure layout pattern by at least one via layout pattern.

16 . The integrated circuit designing system of claim 13 , wherein the set of instructions is for generating that the first interconnect structure layout pattern, the second interconnect structure layout pattern and the third interconnect structure layout pattern are arranged in an L-shape, a T-shape or a comb shape.

17 - 20 . (canceled)

21 . A semiconductor device comprising:
a first interconnect portion having a first width and a first length; a second interconnect portion having a second width and a second length, wherein the second length is less than the first length, and the second interconnect portion is connected to the first interconnect portion; a third interconnect portion having a third width and a third length, wherein the third length is

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Jian-Hong
• Chang Hsin-Chun
• CHEN Shiou-Fan
• Chiu Chwei-Ching
• Lee Yung-Huei

Classifications

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/057 Primary

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title