Multiple processor architecture with flexible external input/output interface

Patent metadata

Field	Value
Publication number	US-2016239455-A1
Application number	US-201514622571-A
Country	US
Kind code	A1
Filing date	Feb 13, 2015
Priority date	Feb 13, 2015
Publication date	Aug 18, 2016
Grant date	—

Abstract

A multiple processor architecture with flexible external input/output interface is provided. In one embodiment, an open flexible processor architecture avionics device comprises: a multiple processor architecture having a primary processor, a secondary processor, a random access memory (RAM) coupled to at least the secondary processor, and a shared memory coupled to the primary and secondary processor; and a flexible input/output (I/O) interface coupled to the multiple processor architecture, wherein the flexible I/O interface provides I/O access to the primary processor using a fixed I/O protocol, and provides I/O access to the secondary processor using at least one re-configurable I/O protocol; wherein the primary processor is dedicated to executing embedded software for implementing a primary base functionality, the primary processor has read and write access to the shared memory, and the primary processor is not reprogrammable; and wherein the secondary processor has read-only access to the shared memory and is programmable.

First claim

What is claimed is:

1 . An open flexible processor architecture avionics device, the device comprising:
a multiple processor architecture having at least a primary processor, at least a secondary processor, a random access memory (RAM) coupled to at least the secondary processor, and a shared memory coupled to the primary processor and the secondary processor; and a flexible input/output (I/O) interface coupled to the multiple processor architecture, wherein the flexible I/O interface provides I/O access to the primary processor using a fixed I/O protocol, and provides I/O access to the secondary processor using at least one re-configurable I/O protocol; wherein the primary processor is dedicated to executing embedded software for implementing a primary base functionality, the primary processor has read and write access to the shared memory, and the primary processor is not reprogrammable; and wherein the secondary processor has read-only access to the shared memory and is programmable.

2 . The device of claim 1 , wherein the flexible I/O interface further comprises:
a first peripheral bus coupled to the primary processor; a second peripheral bus coupled to the secondary processor; and an external I/O arbitrator coupled to the first peripheral bus and the second peripheral bus; wherein the external I/O arbitrator prevents an external host system and the primary processor or the secondary processor to drive the respective first or second peripheral buses simultaneously.

3 . The device of claim 2 , wherein one or both of the first peripheral bus and the second peripheral bus comprise an AMBA Advanced Peripheral Bus (APB) standard peripheral bus.

4 . The device of claim 2 , wherein one or both of the second peripheral bus and the external I/O arbitrator are configured based on signals from the secondary processor.

5 . The device of claim 2 , wherein the second peripheral bus supports I/O access to the secondary processor using at least one of a universal asynchronous receiver transmitter (UART) protocol or an synchronous data link control (SDLC) protocol.

6 . The device of claim 1 , the device further comprising at least one set of inertial sensors coupled to the primary processor, wherein the embedded software for implementing a primary base functionality comprises Inertial Measurement Unit software.

7 . The device of claim 6 , wherein the IMU software saves raw inertial data to the shared memory.

8 . The device of claim 7 , wherein an application executed by the secondary processor accesses the raw inertial data from the shared memory and sends it to an external host system to be processed.

9 . The device of claim 1 , wherein the secondary processor executes an application to interact with a navigation system, a vehicle control system, or a guidance system.

10 . The device of claim 1 , further comprising a non-volatile memory that interacts with the secondary processor and stores data generated by the secondary processor.

11 . The device of claim 10 , wherein the non-volatile memory is an electronically erasable programmable read-only memory or a flash memory.

12 . The device of claim 2 , wherein the flexible external I/O has fourteen pins of which at least two pins are non-configurable.

13 . The device of claim 2 , wherein two or more pins of the flexible external I/O combine to form one or more ports that support single-ended signals.

14 . The device of claim 2 , wherein two or more pins of the flexible external I/O combine to form one or more ports that support differential signals.

15 . A method for an open flexible processor architecture avionics device, the method comprising:
executing a primary base function on a primary processor of the avionics device, wherein the primary processor is non-field-programmable; executing at least one secondary function on a secondary processor of the avionics device, where the secondary processor is field-programmable; sharing data generated by the primary base function with the secondary base function via a memory, wherein the secondary processor has only read-only access to the memory; and operating a flexible input/output (I/O) interface within the avionics device to communicate data between at least one host system and the primary processor, and communicate data between the at least one host system and the secondary processor, wherein the flexible I/O interface implements a fixed I/O protocol to communicate with the primary processor and implements at least one reconfigurable I/O protocol to communicate with the secondary processor, wherein the at least one reconfigurable I/O protocol is configurable by the secondary processor.

16 . The method of claim 15 , wherein the flexible input/output (I/O) interface comprises a first peripheral bus coupled to the primary processor and a second peripheral bus coupled to the secondary processor, the method further comprising:
arbitrating access to the first peripheral bus and the second peripheral bus to prevent the at least one host system from simultaneously accessing the first peripheral bus and the second peripheral bus.

17 . The method of claim 15 , wherein operating the flexible I/O interface further comprises providing a universal asynchronous receiver transmitter (UART) protocol or a synchronous data link control (SDLC) protocol for the second peripheral bus to access the secondary processor.

18 . The method of claim 15 , wherein operating the flexible I/O interface further comprises providing means to combine two or more of the pins to form ports that support one or both of single ended signals and differential signals.

19 . An inertial measurement unit, the unit comprising:
a multiple processor architecture having a primary processing core dedicated to executing embedded IMU software, a secondary processing core that is programmable by an end user and a shared memory component, wherein the primary processing core has read and write access to the shared memory component and the secondary processing core has read-only access to the shared memory component; a flexible input/output (I/O) interface having a first advance peripheral bus (APB), a second advance peripheral bus (APB) and a flexible external input/output (I/O) arbitrator, wherein the first APB interacts with the primary processing core, the second APB interacts with the secondary processing core, and the first APB and the second APB both interact with the external I/O arbitrator.

20 . The inertial measurement unit of claim 19 , wherein the flexible external I/O comprises pins and ports that communicate single ended signals at a +5V level.

Assignees

• Honeywell Int Inc

Inventors

• Merritt Ross
• Matthews Christopher Jay
• Van-Cao Dang Tu
• Lund Christopher A
• Buck Timothy Merrill

Classifications

• G06F13/1663

  Access to shared memory · CPC title

• G06F13/30

  with priority control · CPC title

• G06F13/4226 Primary

  with asynchronous protocol · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G11C7/1072

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title