Systems and methods for providing kernel scheduling of volatile memory maintenance events

Patent metadata

Field	Value
Publication number	US-2016239441-A1
Application number	US-201514621929-A
Country	US
Kind code	A1
Filing date	Feb 13, 2015
Priority date	Feb 13, 2015
Publication date	Aug 18, 2016
Grant date	—

Abstract

Systems, methods, and computer programs are disclosed for scheduling volatile memory maintenance events. One embodiment is a method comprising: a memory controller determining a time-of-service (ToS) window for executing a maintenance event for a volatile memory device coupled to the memory controller via a memory data interface; the memory controller providing an interrupt signal to a processing unit; determining a priority for the maintenance event; and scheduling the maintenance event according to the priority.

First claim

What is claimed is:

1 . A method for scheduling volatile memory maintenance events, the method comprising:
a memory controller determining a time-of-service (ToS) window for executing a maintenance event for a volatile memory device coupled to the memory controller via a memory data interface; the memory controller providing an interrupt signal to a processing unit; determining a priority for the maintenance event; and scheduling the maintenance event according to the priority.

2 . The method of claim 1 , further comprising:
executing the maintenance event for the volatile memory device during the ToS window.

3 . The method of claim 1 , further comprising:
determining that the ToS window has expired without executing the maintenance event; stalling traffic on the processing unit; and executing the maintenance event for the volatile memory device.

4 . The method of claim 1 , wherein the maintenance event comprises one or more of a refresh operation, a calibration operation, and a training operation for periodically servicing the volatile memory device.

5 . The method of claim 1 , wherein the volatile memory device comprises a dynamic random access memory (DRAM) device.

6 . The method of claim 1 , wherein the determining the priority for the maintenance event comprises accessing a look-up table and selecting the priority based on one or more of a type of maintenance event, a current load associated with the processing unit, and a current temperature associated with the volatile memory device.

7 . The method of claim 1 , wherein the scheduling the maintenance event comprises adding a service thread to an input queue associated with a kernel scheduler.

8 . A system for scheduling volatile memory maintenance events, the system comprising:
means for determining a time-of-service (ToS) window for executing a maintenance event for a volatile memory device coupled to a memory controller via a memory data interface; means for providing an interrupt signal to a processing unit; means for determining a priority for the maintenance event; and means for scheduling the maintenance event according to the priority.

9 . The system of claim 8 , further comprising:
means for executing the maintenance event for the volatile memory device during the ToS window.

10 . The system of claim 8 , further comprising:
means for determining that the ToS window has expired without executing the maintenance event; means for stalling traffic on the processing unit; and means for executing the maintenance event for the volatile memory device.

11 . The system of claim 8 , wherein the maintenance event comprises one or more of a refresh operation, a calibration operation, and a training operation for periodically servicing the volatile memory device.

12 . The system of claim 8 , wherein the volatile memory device comprises a dynamic random access memory (DRAM) device.

13 . The system of claim 8 , wherein the means for determining the priority for the maintenance event comprises:
means for accessing a look-up table and selecting the priority based on one or more of a type of maintenance event, a current load associated with the processing unit, and a current temperature associated with the volatile memory device.

14 . The system of claim 8 , wherein the means for scheduling the maintenance event comprises:
means for adding a service thread to an input queue associated with a kernel scheduler.

15 . A computer program embodied in a memory and executable by a processor for scheduling volatile memory maintenance events, the computer program comprising logic configured to:
determine a time-of-service (ToS) window for executing a maintenance event for a volatile memory device coupled to the memory controller via a memory data interface; provide an interrupt signal to a processing unit; determine a priority for the maintenance event; and schedule the maintenance event according to the priority.

16 . The computer program of claim 15 , further comprising logic configured to:
execute the maintenance event for the volatile memory device during the ToS window.

17 . The computer program of claim 15 , further comprising logic configured to:
determine that the scheduled maintenance event has not been executed during the ToS window; stall traffic on the processing unit; and execute the maintenance event for the volatile memory device.

18 . The computer program of claim 15 , wherein the maintenance event comprises one or more of a refresh operation, a calibration operation, and a training operation for periodically servicing the volatile memory device.

19 . The computer program of claim 15 , wherein the volatile memory device comprises a dynamic random access memory (DRAM) device.

20 . The computer program of claim 15 , wherein the logic configured to determine the priority for the maintenance event comprises logic configured to access a look-up table and select the priority based on one or more of a type of maintenance event, a current load associated with the processing unit, and a current temperature associated with the volatile memory device.

21 . The computer program of claim 15 , wherein the logic configured to schedule the maintenance event comprises logic configured to add a service thread to an input queue associated with a kernel scheduler.

22 . A system for scheduling volatile memory maintenance events, the system comprising:
a dynamic random access memory (DRAM) device; a system on chip (SoC) comprising a processing device and a DRAM controller electrically coupled to the DRAM device via a memory data interface, the DRAM controller comprising a scheduler module configured to determine a time-of-service (ToS) window for executing a maintenance event for the DRAM device, the ToS window defined by an interrupt signal provided to the processing device and a deadline for executing the maintenance; and the processing unit configured to:
receive the interrupt signal from the DRAM controller;
in response to the interrupt signal, determine a priority for the maintenance event; and
schedule the maintenance event according to the priority.

23 . The system of claim 22 , wherein the processing unit is further configured to: initiate execution of the maintenance event for the DRAM device during the ToS window.

24 . The system of claim 22 , wherein the DRAM controller comprises a timer for determining whether the ToS window has expired without the maintenance event being executed.

25 . The system of claim 22 , wherein the DRAM controller intervenes to perform the maintenance event if the ToS window expires without the scheduled maintenance event being executed by the processing device.

26 . The system of claim 25 , wherein DRAM controller performs the maintenance event by stalling traffic on the processing device.

27 . The system of claim 22 , wherein the maintenance event comprises one or more of a refresh operation, a calibration operation, and a training operation for periodically servicing the DRAM device.

28 . The system of claim 22 , wherein the processing device determines the priority for the maintenance event by accessing a look-up table and selecting the priority based on one or more of a type of maintenance event, a current load associated with the processing unit, and a current temperature of the

Assignees

• Qualcomm Inc

Inventors

• Chun Dexter Tamio
• Li Yanru

Classifications

• G06F13/18 Primary

  based on priority control (G06F13/1605 takes precedence) · CPC title

• G06F13/26 Primary

  with priority control · CPC title

• G06F9/4818

  Priority circuits therefor · CPC title

• G06F13/1636

  using refresh · CPC title